IP Library › Granted Patent US 7,005,705
Granted Patent B2
US 7,005,705 · App. 10/261,665 · Granted Feb 28, 2006

MOS transistor on an SOI substrate with a body contact and a gate insulating film with variable thickness

Assignee: Renesas Technology Corporation
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Quick Facts
Patent No.
US 7,005,705
App. No.
10/261,665
Granted
Feb 28, 2006
Kind
B2
Abstract

It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film ( 11 ) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate electrode ( 12 ) and an SOI layer ( 3 ), and a gate insulating film ( 110 ) having a thickness of 5 to 15 nm is provided between the gate contact pad (GP) and the SOI layer ( 3 ). The gate insulating film ( 11 ) and the gate insulating film ( 110 ) are provided continuously.

Claims (18)

1. A semiconductor device comprising:

an MOS transistor provided on an SOI layer of an SOI substrate in which a semiconductor substrate, a buried insulating film and said SOI layer are sequentially provided; and

a body contact portion provided in a surface of said SOI layer and capable of fixing an electric potential from an outside,

a gate electrode of said MOS transistor having a shape seen on a plane such that at least one of ends in a direction of a gate width is enlarged in a direction of a gate length to constitute a gate contact pad,

said body contact portion being provided in said surface of said SOI layer on an outside of said end in said direction of said gate width of said gate contact pad and being electrically connected to a channel formation region provided under said gate electrode through said SOI layer,

a gate insulating film of said MOS transistor including a first portion having a first thickness and a second portion having a second thickness in said direction of said gate width,

said second thickness being greater than said first thickness, wherein said second portion of said gate insulating film is provided at least under said gate contact pad, and said first portion and said second portion of said gate insulating film are integrally formed,

an insulating film having said second thickness is provided on said SOI layer to be a connecting portion of said body contact portion and said channel formation region, and

a length in said direction of said gate length of said SOI layer to be said connecting portion of said body contact portion and said channel formation region is smaller than a length obtained by adding a gate length of said gate electrode and a double of a width of a side wall insulating film provided on a side surface of said gate electrode.

2. The semiconductor device according to claim 1 , wherein said insulating film having said second thickness including said second portion of said gate insulating film is provided under said gate contact pad and therearound.

3. The semiconductor device according to claim 2 , wherein a length in said direction of said gate length of said SOI layer to be a connecting portion of said body contact portion and said channel formation region is smaller than a length in said direction of said gate length of said gate contact pad.

4. A semiconductor device comprising:

an MOS transistor provided on an SOI layer of an SOI substrate in which a semiconductor substrate, a buried insulating film and said SOI layer are sequentially provided; and

a body contact portion provided in a surface of said SOI layer and capable of fixing an electric potential from an outside,

a gate insulating film of said MOS transistor including a first portion having a first thickness and a second portion having a second thickness in a direction of a gate width,

said second thickness being greater than said first thickness, and

a gate electrode of said MOS transistor having a shape seen on a plane such that at least one of ends in a direction of a gate width is enlarged in a direction of a gate length to constitute a gate contact pad, wherein said body contact portion is provided in the shape of a band adjacently to a source region of said MOS transistor in said surface of said SOI layer on an outside of an edge portion in said direction of said gate width on the opposite side on which said gate contact pad is provided in said source region,

an insulating film having said second thickness including said second portion of said gate insulating film is provided on one of two ends in said direction of said gate width of said gate electrode of said MOS transistor in which said band-shaped body contact portion is provided.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2004
From: MITSUBISHI DENKI KABUSHIKI KAISHA
To: RENESAS TECHNOLOGY CORP.
Reel/Frame 015185/0122 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 10, 2003
From: MITSUBISHI DENKI KABUSHIKI KAISHA
To: RENESAS TECHNOLOGY CORP.
Reel/Frame 014502/0289 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 2, 2002
From: MAEDA, SHIGENOBU; MATSUMOTO, TAKUJI; IWAMATSU, TOSHIAKI; IPPOSHI, TAKASHI
To: MITSUBISHI DENKI KABUSHIKI KAISHA
Reel/Frame 013356/0031 →
Priority Claims (1)
JP 2002-124180 · Apr 25, 2002 · national
Continuity (1)
Related Publication 20030201494A1 · Oct 30, 2003