IP Library Granted Patent US 6,876,558
Granted Patent B1
US 6,876,558 · App. 10/264,883 · Granted Apr 5, 2005

Method and apparatus for identifying content addressable memory device results for multiple requesting sources

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,876,558
App. No.
10/264,883
Granted
Apr 5, 2005
Kind
B1
Abstract

A system ( 100 ) may include a content addressable memory (CAM) device ( 102 ) and at least two requesting devices ( 104 - 0 and 104 - n ). Requesting devices ( 104 - 0 and 104 - n ) and a CAM device ( 102 ) may be connected by at least two communication links ( 106 - 0 and 106 - n ). A CAM device ( 102 ) may generate responses to requests, and assign a flow identification value for responses based on a communication link ( 106 - 0 and 106 - n ) on which a corresponding request was received.

Claims (48)

1. A content addressable memory (CAM) device, comprising:

at least one CAM array having a plurality of CAM entries; and

a flow identification (ID) generating circuit that generates a flow ID value for a response resulting from a corresponding request, each flow ID value corresponding to an input from which the corresponding request is received.

2. The CAM device of claim 1 , wherein:

the CAM device includes a plurality of input communication links, each input communication link receiving requests from a different requesting source.

3. The CAM device of claim 2 , further including:

a multiplexer that inputs a request from one of a plurality of input communication links.

4. The CAM device of claim 3 , wherein:

the multiplexer inputs a request according to control signals that correspond to flow ID values.

5. The CAM device of claim 1 , further including:

a de-multiplexer that outputs a response on one of a plurality of communication links according to the flow ID value for the response.

6. The CAM device of claim 1 , further including:

a scheduler that generates control signals for inputting request data on one of a plurality of inputs; and

wherein each flow ID values is generated in response to the control signals.

7. The CAM device of claim 6 , further including:

a plurality of first-in-first-out (FIFO) buffer circuits, each coupled to a different input and receiving requests from a different request source and providing status data corresponding to the amount of data in the FIFO buffer circuit to the scheduler.

8. A content addressable memory (CAM) device, comprising:

at least one CAM array;

a de-multiplexer that outputs a response on one of a plurality of output communication links according to at least one flow identification (ID) value associated with the response; and

an input multiplexer that provides a data path between one of a plurality of input communication links and a first data path according to control signals.

9. The CAM device of claim 8 , further including:

a flow ID value generating circuit that generates flow ID values for responses based on an input communication link on which a corresponding request is received.

10. The CAM device of claim 8 , further including:

a select multiplexer having one input coupled to an input data path and another input coupler to the CAM array.

11. The CAM device of claim 10 , further including:

an output store, coupled to an output of the select multiplexer, for storing flow ID values and responses.

12. The CAM device of claim 10 , further including:

an intermediate store for storing flow ID values, the intermediate store being coupled to an input of the select multiplexer.

13. The CAM device of claim 8 , further including:

a plurality of first-in-first-out (FIFO) buffer circuits, each coupled between an output of the de-multiplexer and one of the output communication links.

14. The CAM device of claim 8 , further including:

an input multiplexer that provides a data path between one of a plurality of input communications links and a first data path according to control signals.

15. A method of executing requests in a CAM system, comprising the steps of:

a receiving requests from multiple different sources on input communication links; and

assigning a flow identification (ID) value to a response that corresponds to the input communication link on which a request that generates the response was received.

16. The method of claim 15 , further including the step:

generating responses corresponding to the requests within at least one CAM device.

17. The method of claim 16 , wherein:

the requests are selected from the group consisting of: search operation, read operation, write operation, learn operation, and parity check operations.

18. The method of claim 15 , further including the steps:

storing the flow ID value; and

outputting the flow ID value with response data to an output store.

19. The method of claim 15 , further including the steps:

storing the flow ID value in a first portion of an output store; and

subsequently outputting response data to a second portion of the output store.

20. A content addressable memory (CAM), comprising:

at least one communication link; and

the CAM configured to include flow information to an incoming command corresponding to the link on which the command was received.

Assignments (12)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
CHANGE OF NAME Recorded Apr 16, 2015
From: NETLOGIC MICROSYSTEMS, INC.
To: NETLOGIC I LLC
Reel/Frame 035443/0824 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2015
From: NETLOGIC I LLC
To: BROADCOM CORPORATION
Reel/Frame 035443/0763 →
RELEASE OF SECURITY INTEREST Recorded Sep 26, 2011
From: SILICON VALLEY BANK
To: NETLOGIC MICROSYSTEMS, INC.; NETLOGIC MICROSYSTEMS INTERNATIONAL LIMITED; NETLOGIC MICROSYSTEMS CAYMANS LIMITED
Reel/Frame 026969/0638 →
SECURITY AGREEMENT Recorded Jul 17, 2009
From: NETLOGIC MICROSYSTEMS, INC.; NETLOGIC MICROSYSTEMS INTERNATIONAL LIMITED; NETLOGIC MICROSYSTEMS CAYMANS LIMITED
To: SILICON VALLEY BANK
Reel/Frame 022973/0710 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 26, 2007
From: CYPRESS SEMICONDUCTOR CORPORATION
To: NETLOGIC MICROSYSTEMS, INC.
Reel/Frame 018961/0327 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 28, 2006
From: CYPRESS SEMICONDUCTOR CORPORATION
To: NETLOGIC MICROSYSTEMS, INC.
Reel/Frame 017379/0729 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 10, 2003
From: JAMES, DAVID V.; RAJAMANICKAM, JAGADEESAN
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 013737/0649 →