Magnitude comparator circuit for content addressable memory with programmable priority selection
View Patent ↗A magnitude comparator circuit can include a bitwise comparison section that includes two passgates for each bit of two values that are compared to one another. The passgates can be enabled according to corresponding bit values of the two values.
1. A magnitude comparator circuit, comprising: a bitwise comparison section that includes two passgates for each bit of two values that are compared to one another, the passgates being enabled according to corresponding bit values of the two values.
2. The magnitude comparator circuit of claim 1 , wherein the two values are received from different sub-blocks of a content addressable memory (CAM) device.
3. The magnitude comparator circuit of claim 1 , wherein at least a portion of the two values includes changeable priority values.
4. The magnitude comparator circuit of claim 3 , wherein the changeable priority values may be set by a user of the CAM device.
5. The magnitude comparator circuit of claim 1 , wherein the bitwise comparison section further comprises a first logic circuit to determine the relative magnitude of the bits of the two values and provide a bit magnitude signal indicative of the relative magnitude of the binary values.
6. The magnitude comparator circuit of claim 5 further comprising an equality section in communication with the bitwise comparison section to receive a bit equality signal of each bit of the two values to generate a number equality signal, which when active indicates the equality of the two values.
7. The magnitude comparator circuit of claim 6 further comprising a relative magnitude section in communication with the bit comparison section to receive the bit equality signals and the bit magnitude signals for all bits of the two binary numbers, to logically combine the bit equality signals and the bit magnitude signals to determine the relative magnitude of the two values.
8. The magnitude comparator circuit of claim 1 , wherein the bitwise comparison section further comprises a bit complementing circuit for each bit of the two binary numbers to provide a complement for each bit of the two values.
9. A content addressable memory (CAM) device, comprising: a plurality of sub-blocks each sub-block configured to compare a key value to stored data value; and at least one magnitude comparator for selectively providing an output of one of the plurality of sub-blocks according to associated priority values; wherein
the magnitude comparator comprises
a bit comparison circuit that determines equality for each bit of two binary numbers and if not equal, a relative magnitude for each bit of the two binary numbers.
10. The CAM device of claim 9 , wherein:
the bit comparison circuit comprises:
two passgates for each bit of the two binary numbers that are compared, the passgates being enabled according to corresponding bit values of the two binary numbers to determine equality of the corresponding bits to generate a bit equality signal for each bit of the two binary numbers, and
a first logic circuit to determine the relative magnitude of the bits of the two binary numbers and provide a bit magnitude signal indicative of the relative magnitude of the binary bits;
an equality determination circuit in communication with the bit comparison circuit to receive the bit equality signal of each bit of the two binary numbers to generate a number equality signal, which, when active, indicates the equality of the two binary numbers; and
a relative magnitude circuit in communication with the bit comparison circuit to receive the bit equality signals and the bit magnitude signals for all bits of the two binary numbers, to logically combine the bit equality signals and the bit magnitude signals to determine the relative magnitude of the two binary numbers.
11. The CAM device of claim 10 , wherein the bit comparison circuit further comprises a bit complementer for each bit of the two binary numbers to provide a complement for each bit of the two binary numbers.
12. The CAM device of claim 10 , wherein the two binary numbers include locations of stored data values from different sub-blocks corresponding to the key values received by the CAM device.
13. The CAM device of claim 12 , wherein at least a portion of the key values includes changeable priority values.
14. The CAM device of claim 13 , wherein the changeable priority values may be set by a user of the CAM device.
15. The CAM device of claim 13 further comprising an index selector connected to receive the changeable priority value and the magnitude signal and from the changeable priority signal providing an index signal indicating which one of the binary numbers matches the priority.
16. The CAM device of claim 15 further comprising a multiplexer connected to receive the plurality of input signals and the index signal and dependent upon the index signal provide the output having the one of the plurality of input signals.
17. A method for selecting a result value of a content addressable memory device (CAM), the CAM device having changeable priority values for selecting the result value, the method comprising the steps of:
setting priority values for selecting the result value with a plurality of sub-units of the CAM device;
transferring a comparand to each sub-unit of the CAM device;
comparing the contents of at least one sub-unit of the CAM with the comparand;
providing the result for each of the sub-units;
determining a relative magnitude of the plurality of result values; and
dependent upon the priority values, selecting one of the plurality of result values.
18. The method of claim 17 , wherein the comparand and the changeable priority values are at least a portion of an external transmitted key value.
19. The method of claim 17 , wherein the changeable priority values are set by a user of the content addressable memory device.
20. The method of claim 17 , wherein comparing the contents of at least one sub-unit of the CAM with the comparand comprises the step of the bitwise comparing of the contents of the sub-unit of the CAM with the comparand the bitwise comparing including the step of bitwise complementing for each bit the contents of the sub-unit of the CAM and the comparand to provide a complement for each bit of the contents of the sub-unit of the CAM and the comparand.