Non-volatile semiconductor memory with single layer gate structure
View Patent ↗A semiconductor device of this invention is a single-layer gate nonvolatile semiconductor memory in which a floating gate having a predetermined shape is formed on a semiconductor substrate. This floating gate opposes a diffusion layer serving as a control gate via a gate oxide film and is capacitively coupled with the diffusion layer by using the gate oxide film as a dielectric film. The diffusion layer immediately below the dielectric film is insulated from the semiconductor substrate by an insulating film such as a silicon oxide film. A pair of diffusion layers are formed in surface regions of the semiconductor substrate on the two sides of the floating gate extending on a tunnel oxide film. This invention can realize a reliable semiconductor device which is a single-layer gate semiconductor device by which a low-cost process is possible, has a control gate which can well withstand a high voltage applied when data is erased or written, and can prevent an operation error by minimizing variations in the threshold value.
1. A method of fabricating a semiconductor device, characterized by comprising:
a first step of defining first, second, third, and fourth element active regions by forming an element isolation structure on a semiconductor substrate having an insulating layer in a predetermined depth and covering a region from side surfaces to a lower surface of at least said first element active region with said insulating layer and said element isolation structure;
a second step of forming a first diffusion layer by doping an impurity into said first element active region; the third step of forming a diffusion layer region by doping an impurity having a conductivity type opposite to a conductivity type of said semiconductor substrate into a surface region of said semiconductor substrate in said second element active region;
a fourth step of forming first, second, third, and fourth insulating films on said semiconductor substrate in said first, second, third, and fourth element active regions, respectively;
a fifth step of forming a conductive film via first, second, third, and fourth insulating films on an entire surface of said semiconductor substrate in said first, second, third, and fourth element active regions, respectively;
a sixth step of patterning said conductive film to leave a predetermined pattern in at least one of said first and third element active regions and form gate electrodes in said second and fourth element active regions;
a seventh step of doping an impurity into said third and fourth element active regions to form a pair of second diffusion layers and a pair of third diffusion layers in surface regions of said semiconductor substrate on two sides of said conductive film in said third and fourth element active regions;
an eighth step of doping an impurity having a conductivity type opposite to a conductivity type of said diffusion layer region into said second element active region to form a pair of fourth diffusion layers in surface regions of said semiconductor substrate on two sides of said conductive film in said second element active region;
a ninth step of forming a fifth diffusion layer by doping an impurity into said semiconductor substrate near said third element active region; and
a tenth step of forming an electrode connected to said fifth diffusion layer to apply a predetermined voltage to said third element active region via said fifth diffusion layer.
2. A method of fabricating a semiconductor device, comprising:
a first step of forming a first trench in a surface of a nearly flat semiconductor region;
a second step of forming a first film having a film thickness lager than a depth of said first trench on an entire surface of said semiconductor region to bury said first trench;
a third step of forming a second trench in a portion of said first film above said first trench, said second trench being formed to make a bottom surface of said a second trench lower than said semiconductor substrate except for said first trench and not to reach the surface of said semiconductor substrate in said first trench;
a fourth step of forming a second film having a film thickness larger than a depth of said second trench on an entire surface of said first film to bury said a second trench; and
a fifth step of polishing at least said first and second films by using said semiconductor substrate as a
stopper, thereby planarizing the surface.
3. A method of fabricating a semiconductor device, comprising:
a first step of forming a first insulating film on a semiconductor substrate;
a second step of doping a first impurity to form a first diffusion layer in a predetermined range of a surface region of said semiconductor substrate;
a third step of forming a first conductive film on said first insulating film;
the fourth step of selectively removing said first conductive film until said first insulating film is exposed, thereby forming a first island conductive film on said first diffusion layer and a shield plate electrode having a first hole and a second hole which surrounds said first island conductive film and is wider than said first diffusion layer;
a fifth step of forming a second insulating film on an entire surface to bury said first island conductive film and said shield plate electrode;
a sixth step of defining an element by removing said second insulating film present semiconductor substrate the seventh step of insulating film and a second conductive semiconductor substrate in said element active region;
an eighth step of selectively removing said second conductive film to form a second island conductive film via said third insulating film on said semiconductor substrate in at least said element active region;
a ninth step of doping a second impurity into an entire surface including said element active region to form a pair of second diffusion layers in surface regions of said semiconductor substrate on two sides of said second island conductive film in said element active region; and
a tenth step of forming an integrated floating gate electrode by electrically connecting said first and second island conductive films.
4. A method of fabricating a semiconductor device, comprising:
a first step of forming a first insulating film on a semiconductor substrate;
a second step of doping a first impurity to form a first diffusion layer in a predetermined range of a surface region of said semiconductor substrate;
a third step of forming a first conductive film on said first insulating film;
a fourth step of selectively removing said first conductive film until said first insulating film is exposed, thereby forming a first island conductive film on said first diffusion layer and a shield plate electrode having a first hole and a second hole which surrounds said first island conductive film and is wider than said first diffusion layer;
a fifth step of forming a second insulating film on an entire surface to bury said first island conductive film and said shield plate electrode;
a sixth step of defining an element active region by removing said second insulating film and said first insulating film present in said first hole until said semiconductor substrate is exposed;
a seventh step of forming a third insulating film on said semiconductor substrate in said element active region;
an eighth step of forming a hole which exposes said first island conductive film in said second insulating film;
ninth step of filling said hole by forming a second conductive film on an entire surface including said element active region;
a tenth step of selectively removing said second conductive film so as to leave a pattern extending from said hole to said element active region, thereby forming a floating gate electrode integrated with said first island conductive film; and
an eleventh step of doping a second impurity into said element active region to form a pair of second diffusion layers in surface regions of said semiconductor substrate on two sides of said second conductive film in said element active region.