Semiconductor device and method for manufacturing the same
View Patent ↗A semiconductor device comprises a first Cu interconnect layer, an interlayer insulation film formed thereon, a via hole formed in the interlayer insulation film to expose a part of the first Cu interconnect layer and a Cu via formed within the via hole and connected to the first Cu interconnect layer. A TaN barrier film and a Ta barrier film are laminated on the side surface of the Cu via, and only the Ta barrier film is formed under the bottom surface thereof. The adherence between the TaN barrier film and the interlayer insulation film is strong, and the adherence between the Ta barrier film and copper is strong. Both the barrier films prevent Cu contamination due to diffusion of Cu and at the same time, enhance adherence between Cu and the interlayer insulation film at the side surface of the Cu via to prevent removal of the Cu via.
1. A semiconductor device comprising:
a lower interconnect layer formed of copper or copper alloy;
an interlayer insulation film covering said lower interconnect layer;
a via hole formed in said interlayer insulation film to expose a part of said lower interconnect layer;
a copper via formed by forming copper or copper alloy within said via hole and connected to said lower interconnect layer;
a first barrier film and a second barrier film, both being formed on a side surface of said copper via and laminated relatively to each other, said second barrier film being formed on a bottom surface of said copper via and said first barrier film not being formed on said bottom surface,
wherein said first barrier film is on a side of said interlayer insulation film and adherence between said first barrier film and said interlayer insulation film is stronger than adherence between said first barrier film and said copper via, and said second barrier film is on a side of said copper via and adherence between said second barrier film and said copper via is stronger than adherence between said second barrier film and said interlayer insulation film,
an upper interconnect trench formed in said interlayer insulation film on said copper via; and
an upper interconnect layer made of copper formed within said upper interconnect trench,
wherein said upper interconnect layer and said lower interconnect layer are connected together through said copper via, and wherein both said first and second barrier films are laminated on sides and a bottom of said upper interconnect layer other than where said upper interconnect layer contacts said copper via,
wherein an aspect ratio of said via hole ranges from 1.5 to 5.
2. A semiconductor device comprising:
a lower interconnect layer formed of copper or copper alloy;
an interlayer insulation film covering said lower interconnect layer;
a via hole formed in said interlayer insulation film to expose a part of said lower interconnect layer;
a copper via formed by forming copper or copper alloy within said via hole and connected to said lower interconnect layer;
a first barrier film and a second barrier film, both being formed on a side surface of said copper via and laminated relatively to each other, said second barrier film being formed on a bottom surface of said copper via and said first barrier film not being formed on said bottom surface,
wherein said first barrier film is on a side of said interlayer insulation film and adherence between said first barrier film and said interlayer insulation film is stronger than adherence between said first barrier film and said copper via, and said second barrier film is on a side of said copper via and adherence between said second barrier film and said copper via is stronger than adherence between said second barrier film and said interlayer insulation film,
an upper interconnect trench formed in said interlayer insulation film on said copper via; and
an upper interconnect layer made of copper formed within said upper interconnect trench,
wherein said upper interconnect layer and said lower interconnect layer are connected together through said copper via, and wherein both said first and second barrier films are laminated on sides and a bottom of said upper interconnect layer other than where said upper interconnect layer contacts said copper via,
wherein any one of sets of a TaN film and a Ta film, a TiN film and a Ti film, a WN film and a W film corresponds to a set of said first barrier film and said second barrier film.
3. A semiconductor device comprising:
a lower interconnect layer formed of copper or copper alloy;
an interlayer insulation film covering said lower interconnect layer;
a via hole formed in said interlayer insulation film to expose a part of said lower interconnect layer;
a copper via formed by forming copper or copper alloy within said via hole and connected to said lower interconnect layer;
a first barrier film and a second barrier film, both being formed on a side surface of said copper via and laminated relatively to each other, said second barrier film being formed on a bottom surface of said copper via and said first barrier film not being formed on said bottom surface,
wherein said first barrier film is on a side of said interlayer insulation film and adherence between said first barrier film and said interlayer insulation film is stronger than adherence between said first barrier film and said copper via, and said second barrier film is on a side of said copper via and adherence between said second barrier film and said copper via is stronger than adherence between said second barrier film and said interlayer insulation film,
an upper interconnect trench formed in said interlayer insulation film on said copper via; and
an upper interconnect layer made of copper formed within said upper interconnect trench,
wherein said upper interconnect layer and said lower interconnect layer are connected together through said copper via, and wherein both said first and second barrier films are laminated on sides and a bottom of said upper interconnect layer other than where said upper interconnect layer contacts said copper via,
wherein said first barrier film and said second barrier film each is formed to a film thickness of 10 to 20 nm.
4. A semiconductor device comprising:
a lower interconnect layer formed of copper or copper alloy;
an interlayer insulation film covering said lower interconnect layer;
a via hole formed in said interlayer insulation film to expose a part of said lower interconnect layer;
a copper via formed by forming copper or copper alloy within said via hole and connected to said lower interconnect layer;
a first barrier film and a second barrier film, both being formed on a side surface of said copper via and laminated relatively to each other, said second barrier film being formed on a bottom surface of said copper via and said first barrier film not being formed on said bottom surface,
said first barrier film being positioned on a side of said interlayer insulation film and adherence between said first barrier film and said interlayer insulation film being stronger than adherence between said first barrier film and said copper via, said second barrier film being positioned on a side of said copper via and adherence between said second barrier film and said copper via being stronger than adherence between said second barrier film and said interlayer insulation film;
an upper interconnect trench formed in said interlayer insulation film on said copper via; and
an upper interconnect layer made of copper formed within said upper interconnect trench,
wherein said upper interconnect layer and said lower interconnect layer are connected together through said copper via, said upper interconnect layer and said copper via form one-piece structure consisting of copper to thereby constitute a dual damascene structure, only said second barrier film is formed in a connection region for connecting said lower interconnect layer and said copper via together, and said first and second barrier films are being laminated in a contact region for making said interlayer insulation film and a copper region consisting of said upper interconnect layer and said copper via contact each other, said contact region being defined as a region other than said connection region.
5. A semiconductor device comprising:
a lower interconnect layer formed of copper or copper alloy;
an interlayer insulation film covering said lower interconnect layer;
a via hole formed in said interlayer insulation film to expose a part of said lower interconnect layer;
a copper via formed by forming copper or copper alloy within said via hole and connected to said lower interconnect layer;
a first barrier film and a second barrier film, both being formed on a side surface of said copper via and laminated relatively to each other, said second barrier film being formed on a bottom surface of said copper via and said first barrier film not being formed on said bottom surface,
said first barrier film being positioned on a side of said interlayer insulation film and adherence between said first barrier film and said interlayer insulation film being stronger than adherence between said first barrier film and said copper via, said second barrier film being positioned on a side of said copper via and adherence between said second barrier film and said copper via being stronger than adherence between said second barrier film and said interlayer insulation film;
an upper interconnect trench formed in said interlayer insulation film on said copper via; and
an upper interconnect layer made of copper and formed within said upper interconnect trench,
wherein said upper interconnect layer and said lower interconnect layer are connected together through said copper via, said upper interconnect layer and said copper via are constructed by forming one-piece structure consisting of copper as a dual damascene structure, only said second barrier film is formed under each of bottom surfaces of said upper interconnect layer and said copper via, and said first and second barrier films are being laminated on each of side surfaces of said upper interconnect layer and said copper via.
6. A semiconductor device comprising:
a lower interconnect layer formed of copper or copper alloy;
an interlayer insulation film covering said lower interconnect layer;
a via hole formed in said interlayer insulation film to expose a part of said lower interconnect layer;
a copper via formed by forming copper or copper alloy within said via hole and connected to said lower interconnect layer; and
a first barrier film and a second barrier film, both being formed on a side surface of said copper via and laminated relatively to each other, said second barrier film being formed on a bottom surface of said copper via and said first barrier film not being formed on said bottom surface,
said first barrier film being positioned on a side of said interlayer insulation film and adherence between said first barrier film and said interlayer insulation film being stronger than adherence between said first barrier film and said copper via, said second barrier film being positioned on a side of said copper via and adherence between said second barrier film and said copper via being stronger than adherence between said second barrier film and said interlayer insulation film,
wherein any one of sets of a TaN film and a Ta film, a TIN film and a Ti film, a WN film and a W film corresponds to a set of said first barrier film and said second barrier film.
7. A semiconductor device comprising:
a lower interconnect layer formed of copper or copper alloy;
an interlayer insulation film covering said lower interconnect layer;
a via hole formed in said interlayer insulation film to expose a part of said lower interconnect layer;
a copper via formed by forming copper or copper alloy within said via hole and connected to said lower interconnect layer; and
a first barrier film and a second barrier film, both being formed on a side surface of said copper via and laminated relatively to each other, said second barrier film being formed on a bottom surface of said copper via and said first barrier film not being formed on said bottom surface,
said first barrier film being positioned on a side of said interlayer insulation film and adherence between said first barrier film and said interlayer insulation film being stronger than adherence between said first barrier film and said copper via, said second barrier film being positioned on a side of said copper via and adherence between said second barrier film and said copper via being stronger than adherence between said second barrier film and said interlayer insulation film,
wherein said first barrier film and said second barrier film each is formed to a film thickness of 10 to 20 nm.
8. A semiconductor device comprising:
a lower interconnect layer formed of copper or copper alloy;
an interlayer insulation film covering said lower interconnect layer;
a via hole formed in said interlayer insulation film to expose a part of said lower interconnect layer;
a copper via formed by forming copper or copper alloy within said via hole and connected to said lower interconnect layer, and
a first barrier film and a second barrier film, both being formed on a side surface of said copper via and laminated relatively to each other, said second barrier film being formed on a bottom surface of said copper via and said first barrier film not being formed on said bottom surface,
said first barrier film being positioned on a side of said interlayer insulation film and adherence between said first barrier film and said interlayer insulation film being stronger than adherence between said first barrier film and said copper via, said second barrier film being positioned on a side of said copper via and adherence between said second barrier film and said copper via being stronger than adherence between said second barrier film and said interlayer insulation film,
wherein said first barrier film and said second barrier film each is formed to a film thickness of 10 to 20 nm,
wherein any one of sets of a TaN film and a Ta film, a TiN film and a Ti film, a WN film and a W film corresponds to a set of said first barrier film and said second barrier film.
9. The device according to claim 4 , wherein an aspect ratio of said via hole ranges from 1.5 to 5.
10. The device according to claim 5 , wherein an aspect ratio of said via hole ranges from 1.5 to 5.
11. The device according to claim 6 , wherein an aspect ratio of said via hole ranges from 1.5 to 5.
12. The device according to claim 7 , wherein an aspect ratio of said via hole ranges from 1.5 to 5.