IP Library Granted Patent US 6,862,378
Granted Patent B2
US 6,862,378 · App. 10/279,408 · Granted Mar 1, 2005

Silicon-based high speed optical wiring board

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Quick Facts
Patent No.
US 6,862,378
App. No.
10/279,408
Granted
Mar 1, 2005
Kind
B2
Abstract

An optical wire board which utilizes a silicon substrate as the base for both the optical subassembly and the electrical RF transmitting circuit. An optical fiber is preferably passively aligned to the active optical device mounted on the optical subassembly using a V-groove etched into the silicon (and may include a lens or other optical element positioned between the fiber and the active device). An integrated circuit for coupling the active optical device to external contacts is preferably flip-chip mounted to the silicon substrate upon pads disposed on precisely defined edges around a cavity etched beneath the circuit, the inclusion of the cavity beneath the electrical circuit functioning to minimize the dielectric loading effect of the silicon substrate on the integrated circuit.

Claims (31)

1. An optical wire board comprising:

a silicon-based substrate, said substrate having an electrical transmission line provided thereon;

an active optical device disposed on said silicon-based substrate;

an integrated circuit connected to said electrical transmission line, said integrated circuit being positioned on said silicon substrate over an integrated circuit cavity, wherein said integrated circuit cavity is substantially co-extensive with said integrated circuit to minimize the dielectric loading effect of said silicon substrate on said integrated circuit; and

biasing circuitry disposed on said silicon substrate and connected to said electrical transmission line for operating said active optical device in conjunction with said integrated circuit.

2. The optical wire board of claim 1 wherein the board further comprises an optical subassembly provided on said silicon substrate, said optical subassembly comprising an optical cavity for mounting an optical element and an alignment arrangement for passively aligning said optical element to the active optical device.

3. The optical wire board of claim 2 , wherein the alignment arrangement for passively aligning the optical element to the active optical device comprises a V-shaped groove formed in the optical cavity on the silicon substrate, with a ball lens disposed in said optical cavity on said silicon substrate.

4. The optical wire board of claim 1 , wherein said electrical transmission line contains metallization of one or more constituents selected from the group consisting of Ti, TiN, Pt, Au and Cr.

5. The optical wire board of claim 1 , wherein the biasing circuitry includes integrated resistors, with Ta 2 N used for the integrated resistors.

6. The optical wire board of claim 1 , wherein the biasing circuitry includes integrated capacitors, with a-SiOH:H and/or SiN:H used for the dielectric material in said capacitors.

7. The optical wire board of claim 1 , wherein the integrated circuit is flip-chip mounted to the silicon substrate.

8. The optical wire board of claim 1 , wherein the integrated circuit is mounted on bond pads over edges of the integrated circuit cavity and said bond pads are within at least about 10 μm of said edges of said cavity.

9. The optical wire board of claim 1 wherein the board further comprises an oxide layer with a minimal number of interface states formed between the silicon-based substrate and the electrical transmission line to minimize RF insertion loss.

10. An optical wire board comprising:

a silicon-based substrate, said substrate having an electrical transmission line provided thereon;

an active optical device disposed on said silicon-based substrate;

an integrated circuit connected to said electrical transmission line, said integrated circuit being flip-chip mounted on pads provided on said silicon substrate over an integrated circuit cavity and within at least about 10 μm of the edges of said cavity, wherein said integrated circuit cavity is substantially co-extensive with said integrated circuit to minimize the dielectric loading effect of said silicon substrate on said integrated circuit; and

biasing circuitry disposed on said silicon substrate and connected to said electrical transmission line for operating said active optical device in conjunction with said integrated circuit.

11. The optical wire board of claim 10 , further comprising an optical subassembly provided on the silicon substrate, said optical subassembly comprising an optical cavity for mounting an optical element and an alignment arrangement for passively aligning said optical element to said active optical device.

12. The optical wire board of claim 11 , wherein the alignment arrangement for passively aligning the optical element to the active optical device comprises a V-shaped groove formed in said optical cavity on the silicon substrate and a ball lens disposed in said optical cavity on said silicon substrate.

13. The optical wire board of claim 10 , wherein the electrical transmission line contains metallization of one or more constituents selected from the group consisting of Ti, TiN, Pt, Au and Cr.

14. The optical wire board of claim 10 , wherein the biasing circuitry includes integrated resistors, with Ta 2 N used for said integrated resistors.

15. The optical wire board of claim 10 , wherein the biasing circuitry contains integrated capacitors, with a-SiOH:H and/or SiN:H used for said capacitors.

16. The optical wire board of claim 10 wherein the board further comprises an oxide layer with a minimal number of interface states formed between the silicon-based substrate and the electrical transmission line to minimize RF insertion loss.

17. An optical wire board comprising:

a silicon-based substrate, said substrate having an electrical transmission line provided thereon;

an active optical device disposed on said silicon-based substrate;

an integrated circuit connected to said electrical transmission line, said integrated circuit being positioned on said silicon substrate over an integrated circuit cavity, wherein said integrated circuit cavity is substantially co-extensive with said integrated circuit to minimize the dielectric loading effect of said silicon substrate on said integrated circuit;

biasing circuitry disposed on said silicon substrate and connected to said electrical transmission line for operating said active optical device in conjunction with said integrated circuit; and

an optical subassembly disposed on said silicon substrate, said optical subassembly comprising an optical cavity for mounting an optical element and an alignment means for passively aligning said optical element to said active optical device.

18. The optical wire board of claim 17 wherein the integrated circuit is flip-chip mounted on pads over edges of the integrated circuit cavity and said pads are within at least about 10 μm of said edges of said cavity.

Assignments (5)
MERGER Recorded Jun 16, 2016
From: TRIQUINT SEMICONDUCTOR, INC.
To: QORVO US, INC.
Reel/Frame 039050/0193 →
MERGER Recorded Mar 28, 2011
From: TRIQUINT TECHNOLOGY HOLDING CO., A DELAWARE CORPORATION
To: TRIQUINT SEMICONDUCTOR, INC., A DELAWARE CORPORATION
Reel/Frame 026109/0478 →
MERGER Recorded Oct 26, 2004
From: AGERE SYSTEMS GUARDIAN CORP.
To: AGERE SYSTEMS INC.
Reel/Frame 015296/0327 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2004
From: AGERE SYSTEMS INC.
To: TRIQUINT TECHNOLOGY HOLDING COMPANY
Reel/Frame 015296/0341 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 23, 2002
From: KARNACEWICZ, MARK; OSENBACH, JOHN WILLIAM; PAUNESCU, ALEXANDRU
To: AGERE SYSTEMS GUARDIAN CORP.
Reel/Frame 013434/0812 →