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App. No. 10/281,236 · Confirmation No. 5533

MULTILAYER SEMICONDUCTOR WIRING STRUCTURE WITH REDUCED ALIGNMENT MARK AREA

Inventor: Hirofumi Saito
Patent Expired Due to NonPayment of Maintenance Fees Under 37 CFR 1.362 View Patent ↗ View Publication ↗
⬇ PDF
 Code Description Pages PDF
2003-07-09 IFEE Issue Fee Payment (PTO-85B) 1 View
2002-10-28 TRNA Transmittal of New Application 4 View
2002-10-28 A.PE Preliminary Amendment 2 View
2002-10-28 SPEC Specification 32 View
2002-10-28 CLM Claims 3 View
2002-10-28 ABST Abstract 1 View
2002-10-28 DRW Drawings-only black and white line drawings 18 View
2002-10-28 OATH Oath or Declaration filed 2 View
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Quick Facts
App. No.
10/281,236
Filed
2002-10-28
Granted
2003-09-09
Pub. No.
US20030057452A1
Art Unit
2818
PTA
-120 days