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App. No. 09/877,179 · Confirmation No. 1229

METHOD OF FABRICATION OF MULTILAYERSEMICONDUCTOR WIRING STRUCTURE WITH REDUCED ALIGNMENT MARK AREA

Inventor: Hirofumi Saito
Patent Expired Due to NonPayment of Maintenance Fees Under 37 CFR 1.362 View Patent ↗ View Publication ↗
⬇ PDF
 Code Description Pages PDF
2001-06-11 TRNA Transmittal of New Application 4 View
2001-06-11 SPEC Specification 32 View
2001-06-11 CLM Claims 3 View
2001-06-11 ABST Abstract 1 View
2001-06-11 DRW Drawings-only black and white line drawings 18 View
2001-06-11 OATH Oath or Declaration filed 2 View
2001-06-11 LET. Miscellaneous Incoming Letter 1 View
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Quick Facts
App. No.
09/877,179
Filed
2001-06-11
Granted
2003-02-04
Pub. No.
US20010050437A1
Art Unit
2818
PTA
-2 days