Random access memory (RAM) method of operation and device for search engine systems
View Patent ↗A search engine system ( 100 ) is disclosed that can include at least one content addressable memory (CAM) device ( 102 ) arranged in a cascade configuration with at least one memory device ( 104 ), such as a static random access memory (SRAM). A CAM device ( 102 ) and memory device ( 104 ) may be connected to one another by point-to-point unidirectional connections. Command data issued by a device, such as a network processing unit (NPU) ( 110 ), can flow through all devices beginning with a CAM device ( 102 ) and eventually to a memory device ( 104 ). A memory device ( 104 ) can compare its own current result data with that of a previous device in a flow (such as another RAM device), and generate an output response.
1. A semiconductor memory device, comprising:
at least one output port for providing the command data received by at least one input port and for providing result data generated in response to the command data; and
a memory core that executes indivisible operations in response to predetermined commands, the indivisible operations including writing data to a memory location generated by modifying data read from the memory location.
2. The semiconductor device of claim 1 , wherein:
the output port is a point-to-point connection.
3. The semiconductor device of claim 1 , wherein:
the command data is no more than 8 bits.
4. The semiconductor device of claim 1 , including:
a first vote portion that generates an output result value from at least two input result values, the first vote portion having a first input coupled to the memory core and a second input coupled to the at least one output port.
5. The semiconductor device of claim 4 , further including:
a second vote portion that generates an output result value from at least two input result values, the second vote portion having a first input coupled to a first input port and a second input coupled to a second input port, and an output coupled to the memory core and an input of the first vote portion.
6. The semiconductor device of claim 1 , wherein:
the semiconductor device includes at least two output ports, each output port providing the command data received by at least one input port and the result data generated in response to the command data.
7. The semiconductor device of claim 1 , wherein:
the memory core accesses data values of M*N bits and includes
M data paths, each including N data bits, and
a decoder circuit that selectively enables different numbers of data paths according to lower significance bits of an address.
8. The semiconductor device of claim 1 , wherein:
the memory core includes M data paths, each including N data bits, and
an arithmetic logic unit coupled to the data paths that executes predetermined operations in response to the command data, the predetermined operations being selected from the group consisting of: adding a predetermined value to a data value and in the memory core, logically ORing a predetermined value to a data value stored in the memory core, logically ANDing a predetermined value to a data value stored in the memory core, incrementing a data value stored in the memory core, decrementing a data value stored in the memory core, and outputting a received data value if a data value stored in the memory core has a predetermined value.