Two transistor NOR device
View Patent ↗A NOR gate includes is constructed with two asymmetric FinFET type transistors instead of the conventional four-transistor NOR gate. The reduction in the number of transistors from four down to two allows for significant improvements in integrated semiconductor circuits.
1. A NOR gate comprising:
a first FinFET including first and second independently controllable gate regions, a source region, and a drain region;
a second FinFET including first and second independently controllable gate regions, a source region, and a drain region;
a first input line of the NOR gate connected to the first gate region of the first FinFET and the first gate region of the second FinFET;
a second input line of the NOR gate connected to the second gate region of the first FinFET and the second gate region of the second FinFET; and
an output line of the NOR gate connected to the source of the first FinFET and the drain of the second FinFET.
2. The NOR gate of claim 1 , wherein the first gate regions of the first and second FinFETs are doped with n-type impurities.
3. The NOR gate of claim 2 , wherein the second gate regions of the first and second FinFETs are doped with p-type impurities.
4. The NOR gate of claim 1 , wherein the first and second FinFETs are the only transistors included in the NOR gate.
5. An integrated semiconductor device comprising:
a plurality of asymmetric FinFETs, at least some of the plurality of FinFETs being arranged as pairs of FinFETs that define logic NOR gates.
6. The integrated semiconductor device of claim 5 , wherein the pairs of FinFETs include:
a first FinFET including first and second independently controllable gate regions, a source region, and a drain region; and
a second FinFET including first and second independently controllable gate regions, a source region, and a drain region;
a first input line connected to the first gate region of the first FinFET and the first gate region of the second FinFET;
a second input line connected to the second gate region of the first FinFET and the second gate region of the second FinFET; and
an output line connected to the source of the first FinFET and the drain of the second FinFET.
7. The integrated semiconductor device of claim 6 , wherein the first gate regions of the first and second FinFETs are doped with n-type impurities.
8. The integrated semiconductor device of claim 7 , wherein the second gate regions of the first and second FinFETs are doped with p-type impurities.
9. A logic NOR circuit comprising:
a first asymmetric double-gate transistor; and
a second asymmetric double-gate transistor,
wherein an output signal coupled to the first and second transistors reflects a logical NOR operation of two input signals applied to the first and second transistors.
10. The logic NOR circuit of claim 9 , wherein the first and second asymmetric double-gate transistors are FinFETs.
11. The logic NOR circuit of claim 9 , wherein the first and second asymmetric double-gate transistors each include:
a first gate region;
a second gate region configured to be controllable independently of the first gate region;
a source region; and
a drain region.
12. The logic NOR circuit of claim 11 , wherein the first gate region is doped with n-type impurities.
13. The logic NOR circuit of claim 11 , wherein the second gate region is doped with p-type impurities.