IP Library Granted Patent US 6,960,414
Granted Patent B2
US 6,960,414 · App. 10/305,681 · Granted Nov 1, 2005

Multi-exposure lithography method and system providing increased overlay accuracy

Assignee: Samsung Electronics Co., Ltd.
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Quick Facts
Patent No.
US 6,960,414
App. No.
10/305,681
Granted
Nov 1, 2005
Kind
B2
Abstract

Multi-exposure lithography methods and systems that provide improved overlay accuracy. In one aspect of the invention, a method for multi-exposure lithography comprises determining overlay parameters corresponding to each of a plurality of sub-layouts, inputting the overlay parameters into an exposure system, exposing each sub-layout to photoresist on a wafer by using the exposure system, wherein prior to the exposure process for a given sub-layout, a correction process is performed for the sub-layout using a corresponding overlay parameter to correct an overlay of the sub-layout, and developing the exposed photoresist after exposing all of the sub-layouts.

Claims (43)

1. A multi-exposure lithography method, comprising steps of:

determining overlay parameters for a plurality of sub-layouts of a layout for one layer;

inputting the overlay parameters into an exposure system;

exposing photoresist through each sub-layout on a wafer by using the exposure system, wherein prior to the exposure process for a given sub-layout, a correction process is performed for the sub-layout using a corresponding overlay parameter to correct an overlay of the sub-layout; and

developing the exposed photoresist after exposing the photoresist through all of the sub-layouts.

2. The method of claim 1 , wherein the sub-layouts are arranged on one photomask.

3. The method of claim 2 , wherein the exposing step comprises the step of aligning the wafer, on which the photoresist is coated, and the photomask.

4. The method of claim 1 , wherein the sub-layouts are arranged on a plurality of photomasks.

5. The method of claim 4 , wherein the exposing step further comprises the step of aligning the wafer, on which the photoresist is coated, and a photomask, on which the sub-layout to be exposed is arranged, before each correction process.

6. The method of claim 1 , wherein the overlay parameters for a given sub-layout comprises X-axis and Y-axis offsets, X and Y scales for the wafer, X and Y magnifications for a field, or rotation and orthogonality between the wafer and the field, or any combination thereof.

7. The method of claim 1 , wherein the correction process comprises:

determining a parameter by the exposure system performing an alignment process;

correcting the overlay parameter using the parameter determined by the exposure system to obtain an alignment parameter; and

performing a correction of the overlay using the alignment parameter.

8. A multi-exposure lithography method, comprising the steps of:

forming a plurality of frame-shaped first overlay marks on a border of a die in patterning a first layer on a wafer;

dividing a layout of a second layer into two or more sub-layouts to pattern the second layer on the first layer by a multi-exposure lithography method;

coating photoresist on the wafer, on which the first overlay marks are formed, to pattern the second layer;

exposing the photoresist through the sub-layouts of the layout for the second layer, wherein second overlay marks are formed at locations aligned to each first overlay marks during each exposure process;

determining overlay parameters for the sub-layouts of the layout for the second layer using a measuring system;

inputting the overlay parameters into the exposure system;

exposing the photoresist through each sub-layout to the wafer, on which the first layer is patterned, by using the exposure system, wherein prior to the exposure process for a given sub-layout, a correction process is performed for the sub-layout using a corresponding overlay parameter to correct an overlay of the sub-layout; and

developing the exposed photoresist after exposing the photoresist through all of the sub-layouts.

9. The method of claim 8 , wherein the sub-layouts are arranged on one photomask, and further comprising the step of aligning the photomask and the wafer.

10. The method of claim 8 , wherein the sub-layouts are arranged on a plurality of photomasks, and further comprising the step of aligning the wafer and a photomask, on which the sub-layout to be exposed is arranged, before each correction process.

11. The method of claim 8 , wherein the overlay parameters comprise X-axis and Y-axis offsets, X and Y scales for the wafer, X and Y magnifications for a field, or rotation and orthogonality between the wafer and the field, or any combination thereof.

12. The method of claim 8 , wherein the correction process comprises:

determining a parameter by the exposure system performing an alignment process;

correcting the overlay parameter using the parameter determined by the exposure system to obtain an alignment parameter; and

performing a correction of the overlay using the alignment parameter.

13. A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform the method steps of claim 8 .

14. A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine, to perform method steps for providing multi-exposure lithography, the method steps comprising:

determining overlay parameters for a plurality of sub-layouts of a layout for one layer;

inputting the overlay parameters into an exposure system;

exposing photoresist through each sub-layout on a wafer by using the exposure system, wherein prior to the exposure process for a given sub-layout, a correction process is performed for the sub-layout using a corresponding overlay parameter to correct an overlay of the sub-layout; and

developing the exposed photoresist after exposing the photoresist through all of the sub-layouts.

15. The program storage device of claim 14 , wherein the instructions for performing the exposing step comprise instructions for performing the step of aligning the wafer and the photomask once, when the sub-layouts are all arranged on one photomask.

16. The program storage device of claim 14 , wherein the instructions for performing the exposing step comprise instructions for performing the step of aligning the wafer and a photomask before each correction process, when the sub-layouts are arranged on a plurality of photomasks.

17. The program storage device of claim 14 , wherein the overlay parameters comprise X-axis and Y-axis offsets, X and Y scales for the wafer, X and Y magnifications for a field, or rotation and orthogonality between the wafer and the field, or any combination thereof.

18. The program storage device of claim 14 , wherein the instructions for performing the correction process comprise instructions for performing the steps of:

determining a parameter by the exposure system performing an alignment process;

correcting the input overlay parameter using the parameter determined by the exposure system to obtain an alignment parameter; and

performing a correction of the overlay using the alignment parameter.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2002
From: PARK, JOON-SOO; PARK, CHANG-MIN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 013535/0226 →
Priority Claims (1)
KR 2002-16820 · Mar 27, 2002 · national
Continuity (1)
Related Publication 20030186141A1 · Oct 2, 2003