Access controller that efficiently accesses synchronous semiconductor memory device

1. An access controller that executes in a continuous access mode, the access to columns in the same row of a synchronous semiconductor memory device that has a storage region divided into a plurality of banks, the access controller comprising:

a plurality of last column detection circuits wherein one last column detection circuit is provided corresponding to each of the banks, wherein each of the last column detection circuits detects the access to a last column address in the continuous access mode and generates and outputs a last column detection signal;

a selecting circuit that selects and outputs one last column detection signal from among the last column detection signal output by each of the last column detection circuits based on an address signal; and

an access control section that activates the row of the synchronous semiconductor memory device when the row is accessed in the continuous access mode, outputs a read command or a write command without deactivating the accessed row each time there is a request for access until the last column detection signal output by the selecting circuit is asserted, and deactivates the accessed row when the last column detection signal output by the selecting circuit is asserted.

2. The access controller according to claim 1 , wherein each of the last column detection circuit detects whether the access to the synchronous semiconductor memory device is an access to the last column address of the synchronous semiconductor memory device based on an address signal that is input into the synchronous semiconductor memory device.

3. The access controller according to claim 1 , wherein each of the last column detection circuit detects whether the access to the synchronous semiconductor memory device is an access to the last column address of the synchronous semiconductor memory device based on the comparison of the count of access requests with a predetermined value.

4. The access controller according to claim 1 , further comprising a plurality of access mode registers wherein one access mode register is provided corresponding to each of the banks, wherein each access mode register stores an access mode signal,

wherein the selecting circuit selects and outputs one access mode signal from among the access mode signal stored in each of the access mode registers based on the address signal, and

the access control section identifies whether access is in the continuous access mode based on the access mode signal output by the selecting circuit.

5. The access controller according to claim 1 , wherein

the access control section directly receives an access mode signal from a bus master, and

the access control section identifies whether access is in the continuous access mode based on the access mode signal received by the access control section.

6. The access controller according to claim 1 , further comprising:

a next address calculation unit that calculates and outputs a next address of the address signal; and

an address selecting circuit that selects the address signal to the synchronous semiconductor memory device after a predetermined period after the last column detection signal is asserted, and selects the next address output by the next address calculation section during the predetermined period,

wherein in the continuous access mode, the access control section deactivates the accessed row if the last column detection signal from the select circuit is asserted, and then instantly activates a row indicated by the next address from the next address arithmetic operation section input from the address select circuit.