DC balanced error correction coding
View Patent ↗Two types of codings are integrated, instead of performing each coding independently. The two codings may be integrated by interleaving one or more acts of one coding method (e.g. data coding) between two or more acts of the other coding method (e.g. line coding). In some embodiments, partitioning of a block of data (e.g. a byte) for line coding (e.g. DC balance coding) is done prior to data coding (e.g. error correction coding). In such embodiments, the remaining acts of line coding may be performed after the data coding is completed. In one particular embodiment, an 8 bit byte is not directly used in error correction coding and instead, the 8 bit byte is initially partitioned into two sub-blocks (of 3 bits and 5 bits) as required by 8B/10B encoding (which is an example of line coding). After partitioning, the 8B/10B encoding is not continued, and instead Reed Solomon coding (which is an example of data coding) is then performed (to completion) on the individual sub-blocks (of 3 bits and 5 bits). The error correction coded sub-blocks (of 3 bits and 5 bits) are then used for the remainder of 8B/10B encoding.
1. A method of encoding data by interleaving acts of a data coding method among acts of a line coding method, the method comprising:
(a) performing at least one act of the line coding method on the data to obtain one or more intermediate line coded results;
(b) performing at least one act of the data coding method on the “one or more intermediate line coded results” generated by (a), to obtain one or more data coded results; and
(c) performing at least one act remaining in the line coding method on the “one or more data coded results” generated by (b).
2. The method of claim 1 wherein prior to encoding, the data comprises a plurality of n bit blocks, and wherein:
performance of (a) of claim 1 comprises partitioning each n bit block into a plurality of sub-blocks, each sub-block comprising a plurality of contiguous bits different in number than another sub-block;
performance of (b) of claim 1 comprises applying forward error correction (FEC) encoding to each sub-block independent of another sub-block, to yield a plurality of FEC encoded sub-blocks; and
performance of (c) of claim 1 comprises encoding each FEC encoded sub-block by adding a bit to obtain an output sub-block, wherein at least one bit being added is selected to enhance DC balance across at least a group of output sub-blocks.
3. The method of claim 2 wherein each n bit block is partitioned into two sub-blocks, a sub-block of x bits and a sub-block of n-x bits and performance of (b) of claim 1 comprises:
(x) applying forward error correction (FEC) encoding to the sub-block x bits; and
(y) applying FEC encoding to the sub-block of n-x bits;
wherein act (x) is performed independent of act (y).
4. The method of claim 3 wherein the value of n is 8, and wherein:
FEC encoding in act (x) is performed on a 3 bit sub-block; and
FEC encoding in act (y) is performed on a 5 bit sub-block.
5. The method of claim 4 wherein:
the FEC encoding is Reed-Solomon.
6. The method of claim 5 wherein:
Reed-Solomon encoding for the sub-block of 3 bits uses Galois Field GF8, with a primitive polynomial selected to be either of 1101 and 1011; and
Reed-Solomon encoding for the sub-block of 5 bits uses Galois Field GF32, with a primitive polynomial selected to be any of 101001, 100101, 111101, 111011, 110111 and 101111.
7. The method of claim 6 wherein:
the Reed-Solomon encoding for the sub-block of 3 bits uses generator polynomial; and
the Reed-Solomon encoding for the sub-block of 5 bits uses generator polynomial.
8. The method of claim 7 wherein Reed-Solomon encoding for the sub-block of 3 bits and Reed-Solomon encoding for the sub-block of 5 bits are performed at least partially concurrently.
9. The method of claim 7 wherein during Reed-Solomon encoding for the sub-block of 3 bits,
multiplication with α has
Input
Output
000
000
001
010
010
100
100
011
011
110
110
111
111
101
101
001
and multiplication with α 3 has
Input
Output
000
000
001
011
010
110
100
111
011
101
110
001
111
010
101
100.
10. The method of claim 9 wherein:
each of said multiplications is implemented as a look-up table in memory.
11. The method of claim 9 wherein:
each of said multiplications is implemented as a block of combinational logic.
12. The method of claim 7 wherein during Reed-Solomon encoding for the sub-block of 5 bits,
multiplication with α has
Input
Output
00000
00000
00001
00010
00010
00100
00100
01000
01000
10000
10000
00101
00101
01010
01010
10100
10100
01101
01101
11010
11010
10001
10001
00111
00111
01110
01110
11100
11100
11101
11101
11111
11111
11011
11011
10011
10011
00011
00011
00110
00110
01100
01100
11000
11000
10101
10101
01111
01111
11110
11110
11001
11001
10111
10111
01011
01011
10110
10110
01001
01001
10010
10010
00001
and multiplication with α 18 has
Input
Output
00000
00000
00001
00011
00010
00110
00100
01100
01000
11000
10000
10101
00101
01111
01010
11110
10100
11001
01101
10111
11010
01011
10001
10110
00111
01001
01110
10010
11100
00001
11101
00010
11111
00100
11011
01000
10011
10000
00011
00101
00110
01010
01100
10100
11000
01101
10101
11010
01111
10001
11110
00111
11001
01110
10111
11100
01011
11101
10110
11111
01001
11011
10010
10011.
13. An apparatus for encoding data, the apparatus comprising:
means for partitioning an n bit input block into an x bits sub-block and an n-x bits sub-block, each sub-block consisting of contiguous bits;
means for FEC encoding the x bits sub-block, coupled to the means for partitioning to receive the x bits sub-block therefrom;
means for FEC encoding the n-x bits sub-block, coupled to the means for partitioning to receive the n-x bits sub-block therefrom;
means for encoding the n-x bits sub-block and the x bits sub-block in accordance with 8B/10B encoding, said means for encoding being coupled to each of the means for FEC encoding to receive therefrom FEC encoded n-x bits sub-block and FEC encoded x bits sub-block.
14. The apparatus of claim 13 further comprising:
a serializer coupled to the means for encoding to receive therefrom FEC coded and 8B/10B coded data for supply to a serial link;
a deserializer coupled to the serial link;
means for decoding coupled to the deserializer to decode data in accordance with 8B/10B encoding and generate a decoded x bits sub-block and a decoded n-x bits sub-block;
means for FEC decoding the decoded x bits sub-block, coupled to the means for decoding to receive the decoded x bits sub-block therefrom; and
means for FEC decoding the decoded n-x bits sub-block, coupled to the means for decoding to receive the decoded n-x bits sub-block therefrom;
wherein output from the means for FEC decoding regenerate the n bit input block in case of no errors and also in case of one error in the decoded n-x bits sub-block and one error in the decoded x bits sub-block.
15. The apparatus of claim 13 wherein:
each means for FEC encoding comprises means for Reed Solomon encoding.
16. An apparatus for encoding data, the apparatus comprising:
a line encoding block partitioner having an n bits input bus, an x bits output bus and an n-x bits output bus for carrying an x bits sub-block and an n-x bits sub-block respectively;
an x bits data coder coupled to the x bits output bus to receive therefrom the x bits sub-block;
an n-x bits data coder coupled to the n-x bits output bus to receive therefrom the n-x bits sub-block;
an x bits line coder coupled to the x bits data coder to receive therefrom a data coded x-bit sub-block; and
an n-x bits line coder coupled to the n-x bits data coder to receive therefrom a data coded n-x bits sub-block;
wherein the x bits line coder and the n-x bits line coder are coupled to one another, to transfer a signal therebetween for selection of a bit to be added to at least one of the data coded x bits sub-block and the data coded n-x bits sub-block.
17. The apparatus of claim 16 wherein:
each data coder comprises a look-up table in memory.
18. The apparatus of claim 16 wherein:
one of the data coders uses a primitive polynomial selected to be either of 1101 and 1011.
19. The apparatus of claim 16 further comprising:
a serializer coupled to each of the line coders to receive therefrom data for supply to serial link.
20. The apparatus of claim 16 , wherein:
the line encoding block partitioner comprises an 8B/10B partitioner; and each data coder comprises a Galois Field encoder.