Patent Assignment
Reel/Frame 042423/0183
Merger and Change of Name
Recorded: 2017-05-08
Received: 2017-05-08
Pages: 8
Assignors
APPLIED MICRO CIRCUITS CORPORATION
Executed: 2017-01-26
MACOM CONNECTIVITY SOLUTIONS, LLC
Executed: 2017-01-26
Assignee
MACOM CONNECTIVITY SOLUTIONS, LLC
100 CHELMSFORD STREET, LOWELL, MA, 01851, UNITED STATES
Covered Properties
(73)
Thermal Electric Nand Gate
Application:
12/270,781 →
Thermal Electric nor Gate
Application:
12/120,109 →
Thermal Electric Logic Circuit
Application:
12/040,765 →
Multi-Level Slew and Swing Control Buffer
Application:
11/888,921 →
Modulated Jitter Attenuation Filter
Application:
11/648,920 →
Timeshared Jitter Attenuator in Multi-Channel Mapping Applications
Application:
11/541,176 →
Sampled Accumulation System and Method for Jitter Attenuation
Application:
11/525,656 →
Timer with Periodic Channel Service
Application:
11/402,750 →
Optical Transceiver with Electrical Ring Distribution Interface
Application:
11/395,858 →
Circuit for Adaptive Sampling Edge Position Control and a Method Therefor
Application:
10/984,231 →
High Speed Linear Half-Rate Phase Detector
Application:
10/823,060 →
Modified Gain Non-Causal Channel Equalization Using Feed-Forward and Feedback Compensation
Application:
10/652,333 →
Differential Receiver Circuit with Electronic Dispersion Compensation
Application:
10/638,387 →
High Speed Circuits for Electronic Dispersion Compensation
Application:
10/638,386 →
Differential Receiver Circuit with Electronic Dispersion Compensation for Optical Communications Systems
Application:
10/638,340 →
System and Method for Coding a Digital Wrapper Frame
Application:
10/413,167 →
High-Performance Low-Noise Charge-Pump for Voltage Controlled Oscillator Applications
Application:
10/403,606 →
Loop-Back Clock Phase Generator
Application:
10/402,022 →
10 Gbe Lan Signal Mapping to OTU2 Signal
Application:
10/395,843 →
Digitally Adjusted High Speed Analog Equalizer
Application:
10/394,844 →
Circuit with Voltage Clamping for Bias Transistor to Allow Power Supply Over-Voltage
Application:
10/387,014 →
Phase Adjustment System and Method for Non-Causal Channel Equalization
Application:
10/383,400 →
Dual Voltage-Controlled Oscillator Structure with Power-Down Feature
Application:
10/382,638 →
Serializer with Programmable Delay Elements
Application:
10/382,954 →
Jitter and Wander Reduction Apparatus
Application:
10/346,550 →
Dc Balanced Error Correction Coding
Application:
10/324,615 →
Non-Causal Channel Equalization
Application:
10/317,439 →
Hogge Phase Detector with Adjustable Phase Output
Application:
10/290,127 →
System and Method for Threshold Bias Offset Voltage Cancellation in a Comparator
Application:
10/282,547 →
Feed-Forward/Feedback System and Method for Non-Causal Channel Equalization
Application:
10/262,334 →
System and Method for Half-Rate Clock Phase Detection
Application:
10/218,804 →
System and Method for Voltage Controlled Oscillator Phase Interpolation
Application:
10/218,946 →
System and Method for Comparator Threshold Adjustment
Application:
10/217,215 →
Full Rate Error Detection Circuit for Use with External Circuitry
Application:
10/193,962 →
System and Method for Temporal Analysis of Serial Data
Application:
10/193,961 →
Digital Information Hiding Techniques for Use with Data Streams Carried Over a Data Communication Network
Application:
10/170,994 →
Protocol-Mapping Network Access Device with User-Provisionable Wide Area Network Flow Control
Application:
10/151,792 →
System and Method for Five-Level Non-Casual Channel Equalization
Application:
10/150,301 →
Integrated Xor/Summer/Multiplexer for High Speed Phase Detection
Application:
10/135,415 →
Integrated Xor/Multiplexer for High Speed Phase Detection
Application:
10/135,112 →
Method and Circuit to Reduce Jitter Generation in a Pll Using a Reference Quadrupler and an Equalizer
Application:
10/132,462 →
Method and Circuit to Reduce Jitter Generation in a Pll Using a Reference Quadrupler, Equalizer, and Phase Detector with Control for Multiple Frequencies
Application:
10/132,425 →
Method and Circuit for Producing a Reference Frequency Signal Using a Reference Frequency Doubler Having Frequency Selection Controls
Application:
10/132,463 →
Distributed Clock Network Using All-Digital Master-Slave Delay Lock Loops
Application:
10/120,598 →
No Resonance Mode Bang-Bang Phase Detector
Application:
10/121,013 →
Cascadable Frequency Doubler Having Stable Operation Over Varied Manufacturing Processes and Environmental Operating Conditions
Application:
10/114,835 →
Precision Digital Delay Element Having Stable Operation Over Varied Manufacturing Processes and Environmental Operating Conditions
Application:
10/115,359 →
System to Provide Fractional Bandwidth Data Communications Services
Application:
10/092,064 →
System and Method for Generating a Reference Clock
Application:
10/083,942 →
Configurable Multiplexing Circuit and Method
Application:
10/085,613 →
Configurable Triple Phase-Locked Loop Circuit and Method
Application:
10/085,458 →
System and Method for Non-Causal Channel Equalization Using Error Statistic Driven Thresholds
Application:
10/077,332 →
System and Method for Adjusting a Non-Return to Zero Data Stream Input Threshold
Application:
10/077,274 →
Systems and Methods for Non-Causal Channel Equalization in an Asymmetrical Noise Environment
Application:
10/066,966 →
Wide-Bandwidth Differential Signal Amplifier
Application:
10/061,735 →
Transmission of Data Frames as a Plurality of Subframes Over a Plurality of Channels
Application:
10/054,525 →
System and Method for Measuring Pseudorandom Nrz Data Stream Rates
Application:
10/044,320 →
Buffer Semaphore System and Method
Application:
10/036,951 →
System and Method for Paralleling Digital Wrapper Data Streams
Application:
10/023,675 →
System and Method for Secure Network Provisioning by Locking to Prevent Loading of Subsequently Received Configuration Data
Application:
10/023,019 →
System and Method for Non - Causal Channel Equalization
Application:
10/020,426 →
Parallel Data Bus with Bit Position Encoded on the Clock Wire
Application:
10/016,540 →
Methods and Apparatus for Producing a Reference Frequency Signal with Use of a Reference Frequency Quadrupler Having Frequency Selection Controls
Application:
09/982,156 →
Source Follower for Low Voltage Differential Signaling
Application:
09/966,388 →
Methods and Apparatus for Determining Whether Electronic Devices Are Communicatively Compatible
Application:
09/957,162 →
Pointer Adjustment Wander and Jitter Reduction Apparatus for a Desynchronizer
Application:
09/876,297 →
Pointer Generator Design That Provides Multiple Outputs That Can Be Synchronized to Different Clocks
Application:
09/875,758 →
DS3 Desynchronizer with a Module for Providing Informly Gapped Data Signal to a Pll Module for Providing a Smooth Output Data Signal
Application:
09/825,102 →
Selectable Equalization System and Method
Application:
09/771,241 →
System and Method for Determining Frequency Tolerance Without a Reference
Application:
09/760,132 →
System and Method for Diagnostic Multicast Switching
Application:
09/753,184 →
Bidirectional Line Switch Ring System and Method
Application:
09/753,183 →
System and Method for Redundant Path Connections in Digital Communications Network
Application:
09/753,185 →