Dual voltage-controlled oscillator structure with powder-down feature

1. A multiple voltage-controlled oscillator (“VCO”) structure comprising:

a plurality of VCO circuits, each having a different nominal operating frequency range, and each being configured to provide a respective VCO output signal;

an output selector configured to select one of said respective VCO output signals in response to an output select signal; and

a power-down control architecture configured to regulate power consumption of said plurality of VCO circuits in response to a VCO select signal; wherein said power down control architecture regulates power consumption of said plurality of VCO circuits by selecting bias voltages for bias current transistors utilized by said plurality of VCO circuits; and wherein

said plurality of VCO circuits are realized on one semiconductor chip; and

said different nominal operating frequency ranges facilitate compensation for manufacturing process variation of said semiconductor chip.

2. A VCO structure according to claim 1 , wherein said output select signal is an M-bit signal, and M≧1.

3. A VCO structure according to claim 1 , wherein said output select signal is based upon said VCO select signal.

4. A VCO structure according to claim 3 , wherein said output select signal corresponds to said VCO select signal.

5. A VCO structure according to claim 1 , wherein the nominal operating frequency range of a first VCO circuit from said plurality of VCO circuits overlaps the nominal operating frequency range of at least one other VCO circuit from said plurality of VCO circuits.

6. A VCO structure according to claim 1 , wherein said output selector is a multiplexer.

7. A multiple voltage-controlled oscillator (“VCO”) structure comprising:

a first VCO circuit having a first nominal operating frequency range, said first VCO circuit being configured to provide a first VCO output signal;

a second VCO circuit having a second nominal operating frequency range that overlaps said first nominal operating frequency range, said second VCO circuit being configured to provide a second VCO output signal;

a multiplexer configured to select, in response to a select signal, said first VCO output signal or said second VCO output signal for use as an output; and

a power-down control architecture configured to regulate power consumption of said first VCO circuit and said second VCO circuit in response to said select signal, said power-down control architecture including:

a first power-down controller having a voltage select component configured to provide a first voltage that is sufficient to activate bias current transistor(s) utilized by said first VCO circuit, or a second voltage that is insufficient to activate bias current transistor(s) utilized by said first VCO circuit; and

a second power-down controller having a voltage select component configured to provide a third voltage that is sufficient to activate bias current transistor(s) utilized by said second VCO circuit, or a fourth voltage that is insufficient to activate bias current transistor(s) utilized by said second VCO circuit.

8. A VCO structure according to claim 7 , wherein said power-down control architecture regulates power consumption of said VCO circuits by selecting bias voltages for bias current transistors utilized by said VCO circuits.

9. A VCO structure according to claim 7 , wherein said first VCO circuit and said second VCO circuit are realized on one semiconductor chip.

10. A VCO structure according to claim 9 , wherein said first nominal operating frequency range and said second nominal operating frequency range facilitate compensation for manufacturing process variation of said semiconductor chip.

11. A VCO structure according to claim 7 , wherein:

said first power-down controller provides said first voltage to said first VCO circuit in response to a first logic state of said select signal;

said second power-down controller provides said fourth voltage to said second VCO circuit in response to said first logic state of said select signal;

said first power-down controller provides said second voltage to said first VCO circuit in response to a second logic state of said select signal; and

said second power-down controller provides said third voltage to said second VCO circuit in response to said second logic state of said select signal.

12. A VCO structure according to claim 11 , further comprising an inverter having an input for said select signal and an output for providing an inverted select signal to said second power-down controller.

13. A method for generating a voltage-controlled oscillator (“VCO”) output, said method comprising:

designating a valid VCO circuit, from a plurality of VCO circuits, each having a different nominal operating frequency range, and each being configured to provide a respective VCO output signal;

activating said valid VCO circuit in response to a VCO select signal;

deactivating said plurality of VCO circuits, other than said valid VCO circuit, in response to said VCO select signal;

generating an active VCO output signal with said valid VCO circuit; and

selecting said active VCO output signal; wherein said activating and deactivating of said plurality of VCO circuits is done by generating bias voltages for bias current transistors utilized by said plurality of VCO circuits; and wherein

said plurality of VCO circuits are realized on one semiconductor chip; and

said different nominal operating frequency ranges facilitate compensation for manufacturing process variation of said semiconductor chip.

14. A method according to claim 13 , wherein said activating and deactivating steps regulate power consumption of said plurality of VCO circuits in response to said VCO select signal.

15. A method according to claim 13 , wherein activating said valid VCO circuit comprises:

generating a voltage that is sufficient to activate bias current transistor(s) utilized by said valid VCO circuit; and

providing said voltage to said bias current transistor(s).

16. A method according to claim 13 , wherein deactivating said plurality of VCO circuits comprises:

generating a voltage that is insufficient to activate bias current transistor(s) utilized by said plurality of VCO circuits; and

providing said voltage to said bias current transistor(s).

17. A method according to claim 13 , wherein said active VCO output signal is selected in response to an output select signal.

18. A method according to claim 17 , wherein said output select signal is based upon said VCO select signal.

19. A method according to claim 18 , wherein said output select signal corresponds to said VCO select signal.

20. A method according to claim 13 , wherein the nominal operating frequency range of a first VCO circuit from said plurality of VCO circuits overlaps the nominal operating frequency range of at least one other VCO circuit from said plurality of VCO circuits.

21. A multiple voltage-controlled oscillator (“VCO”) structure comprising:

a plurality of VCO circuits realized on one semiconductor chip, each having a different nominal operating frequency range to facilitate compensation for manufacturing process variation of said semiconductor chip, and each being configured to provide a respective VCO output signal;

a power-down control architecture configured to activate a first VCO circuit from said plurality of VCO circuits and to deactivate said plurality of VCO circuits other than said first VCO circuit, in response to a VCO select signal; wherein said power down control architecture regulates power consumption of said plurality of VCO circuits by selecting bias voltages for bias current transistors utilized by said plurality of VCO circuits; and

an output selector configured to select, in response to an output select signal, a first VCO output signal from said respective VCO output signals, said first VCO output signal being generated by said first VCO circuit.