Precise exit logic for removal of security overlay of instruction space
View Patent ↗A circuit generally comprising a first memory, a processor and a logic block is disclosed. The first memory may store (i) a write instruction to store a non-highest security value of at least three security values in a register and (ii) a jump instruction to a second memory. The processor may have a pipeline and may be configured to (i) bootstrap to the first memory while the register stores a highest security value of the security values and (ii) execute the jump instruction following the write instruction. The logic block may be configured to (i) detect the write instruction in an execution stage of the pipeline and (ii) store the non-highest security value in the register in response to detecting the write instruction in a write back stage of the pipeline.
1. A circuit comprising:
a register;
a first nonvolatile memory configured to store (i) a write instruction to store a non-highest security value of at least three security values in said register and (ii) a jump instruction to jump to a second memory;
a processor having a pipeline and configured to (i) bootstrap to said first nonvolatile memory while said register stores a highest security value of said security values and (ii) execute said jump instruction following said write instruction; and
a logic block configured to (i) detect said write instruction in an execution stage of said pipeline and (ii) store said non-highest security value in said register in response to detecting said write instruction in a write back stage of said pipeline.
2. The circuit according to claim 1 , wherein said logic block is further configured to mimic said pipeline to detect said write instruction both in said execution stage and in said write back stage in said processor.
3. The circuit according to claim 1 , wherein said first nonvolatile memory is uncached by said processor.
4. The circuit according to claim 1 , wherein said processor is further configured to reset to a state in which interrupts are disabled.
5. The circuit according to claim 1 , wherein a default value of said register comprises said highest security value.
6. The circuit according to claim 1 , further comprising a decoder configured to decode an address range for said first nonvolatile memory.
7. The circuit according to claim 1 , wherein said register is further configured to store said security values in at least four bits.
8. The circuit according to claim 7 , further comprising a flag module configured to decode said at least four bits into (i) a first signal corresponding to said highest security value and (ii) a second signal corresponding to an intermediate security value of said security values.
9. The circuit according to claim 1 , further comprising a third memory configured to store information related to security of said circuit.
10. The circuit according to claim 9 , wherein (i) said first nonvolatile memory, said processor, said circuit and said register are part of a first chip, (ii) said second memory is part of a second chip and (iii) said third memory is part of a third chip packaged with said first chip.
11. A method for operating a circuit, comprising the steps of:
(A) bootstrapping a processor to a first memory while in a highest security mode of at least three security modes;
(B) detecting a write instruction that sets a non-highest security mode of said security modes in an execution stage of an instruction pipeline in said processor;
(C) asserting said non-highest security mode in response to detecting said write instruction in a write back stage of said instruction pipeline; and
(D) executing a jump instruction to jump to a second memory.
12. The method according to claim 11 , further comprising the step of:
asserting an intermediate security mode of said security modes in response to an instruction fetch from outside said first memory prior to step (D).
13. The method according to claim 12 , further comprising the step of:
disabling access to said first memory while in said intermediate security mode.
14. The method according to claim 11 , further comprising the step of:
executing a non-operation instruction in said processor before executing any instruction from said second memory in said processor to provide time to exit said highest security mode.
15. The method according to claim 11 , further comprising the step of:
checking for programming in a third memory prior to step (D).
16. The method according to claim 15 , wherein step (C) comprises the sub-step of:
asserting a lowest security mode of said security modes in response to finding said third memory unprogrammed.
17. The method according to claim 15 , further comprising the step of:
reading from said third memory prior to step (D) in response to finding said third memory programmed.
18. The method according to claim 17 , further comprising the step of:
disabling access to said third memory in response to asserting an intermediate security mode of said security modes.
19. The method according to claim 11 , further comprising the step of:
setting up a driver for an interface to a third memory using instructions from said first memory.
20. A system comprising:
means for bootstrapping to a first memory while in a highest security mode of at least three security modes;
means for detecting a write instruction that sets a non-highest security mode of said security modes in an execution stage of an instruction pipeline;
means for asserting said non-highest security mode in response to said write instruction in a write back stage of said instruction pipeline; and
means for executing a jump instruction to a second memory.