Granted Patent B2

US 6,870,214 · App. 10/329,898 · Granted Mar 22, 2005

Abstract

Claims (11)

1. A method for fabricating an EEPROM cell, which comprises the steps of:

providing a silicon substrate;

forming a pad oxide on the silicon substrate so that the silicon substrate is partially exposed;

forming a silicon pillar layer on the silicon substrate wherein the silicon pillar layer is forming, using the exposed surface of the silicon substrate as a seed, according to an anisotropic epitaxial process;

forming a tunneling insulating film and a floating electrode on the sidewall of the silicon pillar layer;

successively forming a control gate insulating film and a control gate electrode on the sidewall of the floating electrode;

forming a source region and a drain region in the silicon substrate at a portion below the side of the control gate electrode, and on the upper surface of the silicon pillar layer, respectively; and

forming bit lines on the drain region.

2. The method of claim 1 , which additionally comprises the steps of forming a hot carrier generation-accelerating region made of a boron-doped epitaxial layer below the drain region.

3. The method of claim 1 , in which the silicon pillar layer is an epitaxial silicon layer.

4. The method of claim 1 , in which the step of forming the bit lines on the drain region comprises the sub-steps of forming an isolating oxide film on the entire structure including the drain; planarizing the isolating oxide film in such a manner that the surface of the drain region is exposed; depositing a conducting layer for forming the bit lines, on the isolating oxide film including the surface of the drain region; selectively patterning the conducting layer to form the bit lines.

Assignments (8)