IP Library Assignment 016069/0777
Patent Assignment
Reel/Frame 016069/0777

Change of Name

Recorded: 2005-04-14 Received: 2005-04-14 Pages: 11
Assignor
DONGBU ELECTRONICS CO., LTD.
Executed: 2004-12-21
Assignee
DONGBUANAM SEMICONDUCTOR INC.
891-10, DAECHI-DONG, KANGNAM-GU, SEOUL, KRX, 135-280, KOREA, REPUBLIC OF
Covered Properties (36)
Apparatus and method for fabricating semiconductor devices
Application: 10/921,054 →
Mask Rom, and Fabrication Method Thereof
Application: 10/803,422 →
Semiconductor Package and Fabrication Method of the Same
Application: 10/614,671 →
Dynamic Random Access Memory and the Method for Fabricating Thereof
Application: 10/391,046 →
Micro-Pattern Forming Method for Semiconductor Device
Application: 10/338,506 →
Method of Fabricating Flash Eeprom
Application: 10/329,898 →
Method for Fabricating a Semiconductor Device
Application: 10/329,587 →
Semiconductor Device Having Trench Capacitor and Method for Fabricating the Same
Application: 10/329,096 →
Method for Forming Fuse in Semiconductor Device
Application: 10/329,097 →
Method for the Fabrication of a Semiconductor Device Utilizing Simultaneous Formation of Contact Plugs
Application: 10/324,304 →
Semiconductor Device and Fabricating Method Thereof
Application: 10/325,381 →
Method for Fabricating Semiconductor Transistor Device
Application: 10/325,120 →
Semiconductor Device and Method for Fabricating the Same
Application: 10/325,392 →
Cylinder type transistor with vertical silicon-on-insulator structure and fabrication method thereof
Application: 10/325,288 →
Short Channel Transistor Fabrication Method for Semiconductor Device
Application: 10/323,328 →
Transistor Fabrication Method
Application: 10/323,330 →
Method of Fabricating Mask Rom
Application: 10/323,329 →
Vertical Type Transistor and Method for Fabricating the Same
Application: 10/323,427 →
Method for Forming Wiring in Semiconductor Device
Application: 10/323,021 →
Method for Forming Isolation Layer in Semiconductor Device
Application: 10/322,849 →
Method for Fabricating Highly Integrated Transistor
Application: 10/323,056 →
Method for Forming Isolation Region in Semiconductor Device
Application: 10/320,124 →
Apparatus and Method for Fabricating Semiconductor Devices
Application: 10/306,238 →
Method for Formation of Copper Diffusion Barrier Film Using Aluminum
Application: 10/306,491 →
Method for Fabricating Semiconductor Device
Application: 10/293,741 →
Method for Fabricating a Silicide Layer of Flat Cell Memory
Application: 10/235,773 →
Method for Manufacturing Mask Rom
Application: 10/201,860 →
Method of post treatment for a metal line of semiconductor device
Application: 10/180,735 →
Method and Apparatus for Manufacturing a Barrier Layer of Semiconductor Device
Application: 10/180,754 →
Method for Manufacturing a Silicide Layer of Semiconductor Device
Application: 10/180,760 →
Semiconductor Package and Fabrication Method of the Same
Application: 10/167,702 →
Method of Manufacturing a Multi-Chip Semiconductor Package
Application: 10/167,558 →
Mask Rom, and Fabrication Method Thereof
Application: 10/039,364 →
Method for Fabricating Mask Rom
Application: 10/053,381 →
Semiconductor Package Having Metal-Pattern Bonding and Method of Fabricating the Same
Application: 09/858,408 →
Assembly Process
Application: 09/801,559 →