Electronic apparatus with ROM data correction function
View Patent ↗An electronic apparatus has in a CPU core an instruction correcting circuit that includes memory cells, a comparator and a selector. The memory cells store, when initializing the electronic apparatus, a correction address, a correction instruction and a correction enabling bit, which are associated with contents of a read-only memory. The comparator compares an instruction address output from an instruction prefetch stage of the CPU core with the correction address stored in the memory cells. The selector selects either an instruction code read from the instruction address of the read-only memory or the correction instruction stored in the memory cells in response to a compared result of the comparator. The electronic apparatus can correct the ROM data after manufacturing without reducing the number of available interrupts or the operation speed of the CPU.
1. An electronic apparatus including a CPU core for carrying out pipeline processing according to data read via a data bus from a read-only memory that stores specified fixed data, said electronic apparatus including an instruction correcting circuit in said CPU core, said instruction correcting circuit comprising:
a set of memory cells for storing, when initializing said electronic apparatus, a correction address, a correction instruction and a correction enabling bit, which are associated with contents of said read-only memory;
a comparator for comparing an instruction address output from an instruction prefetch stage of said CPU core with the correction address stored in said memory cells; and
a selector for selecting one of an instruction code read from the instruction address of said read-only memory and the correction instruction stored in said memory cells in response to a compared result of said comparator wherein said instruction correcting circuit is placed between the instruction prefetch stage and an instruction decoding stage in said CPU core.
2. The electronic apparatus according to claim 1 , wherein said instruction correcting circuit is placed between a memory bus interface and the instruction prefetch stage in said CPU core.
3. The electronic apparatus according to claim 1 , wherein said instruction correcting circuit comprises n sets of memory cells, n comparators, and an encoder for generating a select signal in response to outputs of said n comparators, where n is an integer greater than one, and wherein said selector selects one of the instruction code read from the instruction address of said read-only memory and the correction instructions stored in said n set of memory cells in response to the select signal.
4. An electronic apparatus including a CPU core for carrying out pipeline processing according to data read via a data bus from a read-only memory that stores specified fixed data, said electronic apparatus including a data correcting circuit in said CPU core, said data correcting circuit comprising:
a set of memory cells for storing, when initializing said electronic apparatus, a correction address, correction data and a correction enabling bit, which are associated with contents of said read-only memory;
a comparator for comparing a data address output from a data processing stage of said CPU core with the correction address stored in said memory cells; and
a selector for selecting one of data read from the data address of said read-only memory with the correction data stored in said memory cells in response to a compared result of said comparator, wherein said data correcting circuit is placed between a memory access stage and a register write-back stage in said CPU core.
5. The electronic apparatus according to claim 4 , wherein said data correcting circuit is placed between a memory bus interface and a memory access stage.
6. The electronic apparatus according to claim 4 , wherein said data correcting circuit comprises n sets of memory cells, n comparators, and an encoder for generating a select signal in response to outputs of said n comparators, where n is an integer greater than one, and wherein said selector selects one of the data read from the data address of said read-only memory and the correction data stored in said n set of memory cells in response to the select signal.