Semiconductor device including active regions and gate electrodes for field effect transistors, with a trench formed between the active regions
View Patent ↗A semiconductor device has p-channel field effect transistors disposed in a lattice shape. In order to generate compression stress in the channel of a p-channel field effect transistor, a long active region of a plurality of transistors is divided for each gate electrode and a sufficiently thin shallow trench isolation (STI) is formed between adjacent gate electrodes. The drain current characteristics can be improved.
1. A semiconductor device comprising
a semiconductor substrate;
a plurality of gate electrodes constituting p-channel field effect transistors formed in and on said semiconductor substrate; and
a plurality of spatially arranged active regions formed with areas intersected by portions of said gate electrodes, respectively, to constitute said p-channel field effect transistors together with said plurality of gate electrodes,
wherein:
said plurality of gate electrodes include a first gate electrode and a second gate electrode having a longitudinal direction the same as a longitudinal direction of said first gate electrode, and said first and second gate electrodes are juxtaposed;
said plurality of active regions include a first active region including an area intersected by a portion of said first gate electrode and a second active region including an area intersected by a portion of said second gate electrode; and
a trench is formed between said first and second active regions along said longitudinal direction of said first and second electrodes, and formed along with said first and second active regions in a traverse direction of said longitudinal direction, a width of said trench formed in the traverse direction of said longitudinal direction being wider than that of said trench formed along said longitudinal direction,
wherein the width of said trench formed between said first and second active regions in said longitudinal direction of said first and second electrodes is 0.25 μm or narrower.
2. A semiconductor device comprising:
a semiconductor substrate;
a plurality of gate electrodes constituting p-channel field effect transistors formed in and on said semiconductor substrate; and
a plurality of spatially arranged active regions formed with areas intersected by portions of said gate electrodes, respectively, to constitute said p-channel field effect transistors together with said plurality of gate electrodes,
wherein:
said plurality of gate electrodes include a first gate electrode and a second gate electrode having a longitudinal direction the same as a longitudinal direction of said first gate electrode, and said first and second gate electrodes are juxtaposed;
said plurality of active regions include a first active region including an area intersected by a portion of said first gate electrode and a second active region including an area intersected by a portion of said second gate electrode; and
a trench is formed between said first and second active regions along said longitudinal direction of said first and second electrodes, and formed along with said first and second active regions in a traverse direction of said longitudinal direction, a width of said trench formed in the traverse direction of said longitudinal direction being wider than that of said trench formed along said longitudinal direction, further comprising:
a third active region, arranged in said longitudinal direction relative to said first active region, including an area intersected by a portion of said first gate electrode, said third active region being separated from said first active region by said trench formed in the traverse direction of said longitudinal direction, said third active region constituting a p-channel field effect transistor together with said first gate electrode,
wherein a distance between said first and third active regions is set longer than a distance between said first and second active regions.
3. A semiconductor device according to claim 2 wherein said plurality of active regions are arranged in an array-like structure.
4. A semiconductor device comprising:
a semiconductor substrate;
a plurality of gate electrodes constituting p-channel field effect transistors formed in and on said semiconductor substrate; and
a plurality of array-like laterally and vertically arranged active regions formed with areas intersected by portions of said gate electrodes, respectively, each of said active regions being arranged with a predetermined space, to respectively constitute said p-channel field effect transistors together with said plurality of gate electrodes
wherein:
said plurality of gate electrodes are extended through vertically arranged active regions, respectively;
each of said vertically arranged active regions includes an area intersected by a portion of one of said gate electrodes; and
trenches are laterally formed between said vertically arranged active regions and vertically formed between laterally arranged active regions, a width of said laterally formed trench being wider than that of said vertically formed trench.
5. A semiconductor device according to claim 4 , wherein the width of said vertically formed trench is equal to or less than 0.25 μm.
6. A semiconductor device according to claim 4 , wherein a width of said gate electrode is equal to or less than 0.25 μm.
7. A semiconductor device comprising;
a semiconductor substrate;
a plurality of gate electrodes, constituting channel field effect transistors, formed in and on said semiconductor substrate; and
a plurality of spatially arranged active regions formed with areas intersected by portions of said gate electrodes, respectively, to constitute said p-channel field effect transistors together with said plurality of gate electrodes,
wherein:
said plurality of gate electrodes include a first gate electrode and a second gate electrode having a longitudinal direction the same as a longitudinal direction of said first gate electrode;
said plurality of active regions include a first active region including an area intersected by a portion of said first gate electrode and a second active region including an area intersected by a portion of said second gate electrode; and
a third active region formed with areas intersected by portions of said first and second gate electrodes, respectively, to constitute n-channel field effect transistors together with said first and second gate electrodes,
wherein:
a dummy active region located between the first active region and a fourth active region, which constitutes a p-channel field effect transistor, said fourth active region being located along a traverse direction of said longitudinal direction relative to said first active region;
a first trench formed between the dummy active region and the first active region;
a fifth active region located adjacent to said third active region to constitute an n-channel field effect transistor, said fifth active region being located along said direction traverse to the longitudinal direction relative to said third active region; and
a second trench located between the third active region and the fifth active region,
wherein a width of said first trench is less than a width of said second trench.