IP Library Granted Patent US 7,088,614
Granted Patent B2
US 7,088,614 · App. 10/331,161 · Granted Aug 8, 2006

Programming method for a multilevel memory cell

Assignee: STMicroelectronics S.r.l.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,088,614
App. No.
10/331,161
Granted
Aug 8, 2006
Kind
B2
Abstract

A programming method of a multilevel memory cell is able to store a plurality of bits in a plurality of levels. The method includes writing a logic value in the multilevel memory cell by setting one of the programming levels thereof, these levels being included in the plurality of levels, with respect to a reference level according to the symbol to be written and to a previous programming level. The writing step is repeated until a highest possible value for the levels is reached. A multilevel memory device includes a plurality of multilevel memory cells organized into sectors, split into a plurality of data units whereon a programming operation is performed in parallel.

Claims (51)

1. A programming method for a multilevel memory cell able to store a plurality of bits in a plurality of levels, the method comprising: writing a logic value in said multilevel memory cell by setting a programming level of the cell at one of said plurality of levels with respect to a reference level based on a symbol to be written and on a previous programming level, wherein said writing step is repeated until a highest possible value for said levels is reached, wherein the reference level is stored in an auxiliary cell.

2. The programming method according to claim 1 , wherein said programming level of said cell to be programmed is set according to the following relation:

when writing a first logic value, said programming level of said cell is set equal to the reference level;

when writing a second logic value, said programming level of said cell is set greater than said reference level.

3. The programming method according to claim 2 , wherein said programming level of said cell to be programmed is set according to the following relation:

starting from equal levels of the programming level and the reference level, a writing operation of said first logic value does not involve any increase in said programming level and of said reference level, while writing said second logic value involves an increase in said programming level of said cell to be programmed;

starting from a programming level of said cell to be programmed higher than said reference level, a writing operation of said second logic value does not involve any increase in said programming level and in said reference level, while a writing operation of said first logic value involves an increase in said reference level to bring said levels back to parity conditions;

starting from a programming level of said cell to be programmed lower than said reference level, a writing operation of said first logic value involves an increase in said programming level of said cell to be programmed which brings said levels back to parity conditions, while a writing operation of said second logic value “1” involves a double increase in said programming level of said cell to be programmed to bring said programming level above said reference level.

4. The programming method according to claim 1 , further comprising: erasing said memory cell and resetting updated data only when said highest possible value is reached.

5. The programming method according to claim 1 , wherein said highest possible value is equal to the number of levels in said plurality of levels less 1.

6. A multilevel memory device, comprising:

a memory array including a plurality of multilevel memory cells each able to store a plurality of bits in a plurality of levels, the memory array being organized into a plurality of data units each data unit including an active cell and an auxiliary cell having a level corresponding to a reference level; and

programming means for writing a logic value in a selected one of the data units by setting a programming level of the selected data unit at one of said plurality of levels with respect to the reference level based on a symbol to be written in the data unit and on a previous programming level.

7. The multilevel memory device according to claim 6 , wherein said reference level of said auxiliary cell is initially set at a value corresponding to a lowest possible level.

8. The multilevel memory device according to claim 6 , wherein said reference level of said auxiliary cell and said programming level of said data unit are increased differentially according to the symbol to be written and to a previous programming level without performing an erasing operation until said reference level reaches a highest possible value.

9. The multilevel memory device according to claim 8 , wherein, when said reference level reaches said highest possible value, said programming means performs updated data erasing and resetting steps on said data unit, including on said auxiliary cell, the level of the auxiliary cell being reset at an initial value.

10. The multilevel memory device according to claim 6 , wherein said data unit comprises only one active cell in addition to said auxiliary cell.

11. The multilevel memory device according to claim 6 , wherein said data unit comprises a plurality of active cells to be programmed in addition to the auxiliary cell, the levels of the active cells and auxiliary cell being increased differentially according to the symbol to be written and to the previous programming levels without performing an erasing operation until said reference level reaches a highest possible value.

12. A multilevel memory device, comprising:

a memory array including a plurality of multilevel memory cells each able to store a plurality of bits in a plurality of levels, the memory array being organized into a plurality of data units, each data unit including an active cell and an auxiliary cell having a level corresponding to a reference level; and

programming means for writing a logic value in a selected one of the data units by increased differentially the levels of the active cell and auxiliary cell according to a symbol to be written and according to previous programming levels without performing an erasing operation until said reference level reaches a highest possible value.

13. The device of claim 12 , wherein said reference level of said auxiliary cell is initially set at a value corresponding to a lowest possible level.

14. The device of claim 12 , wherein, when said reference level reaches said highest possible value, said programming means performs updated data erasing and resetting steps on said data unit, including on said auxiliary cell, the level of the auxiliary cell being reset at an initial value.

15. The device of claim 12 , wherein said selected data unit comprises only one active cell in addition to said auxiliary cell.

16. The device of claim 12 , wherein said selected data unit comprises a plurality of active cells to be programmed in addition to the auxiliary cell, the levels of the active cells and auxiliary cell being increased differentially according to the symbol to be written and to the previous programming levels without performing an erasing operation until said reference level reaches the highest possible value.

17. A programming method for a multilevel memory cell able to store a plurality of bits in a plurality of levels, the method comprising: writing a logic value in said multilevel memory cell by setting a programming level of the cell at one of said plurality of levels with respect to a reference level based on a symbol to be written and on a previous programming level, wherein said writing step is repeated until a highest possible value for said levels is reached, wherein said programming level of said cell to be programmed is set according to the following relation:

when writing a first logic value, said programming level of said cell is set equal to the reference level;

when writing a second logic value, said programming level of said cell is set greater than said reference level.

18. The programming method according to claim 17 , wherein said programming level of said cell to be programmed is set according to the following relation:

starting from equal levels of the programming level and the reference level, a writing operation of said first logic value does not involve any increase in said programming level and of said reference level, while writing said second logic value involves an increase in said programming level of said cell to be programmed;

starting from a programming level of said cell to be programmed higher than said reference level, a writing operation of said second logic value does not involve any increase in said programming level and in said reference level, while a writing operation of said first logic value involves an increase in said reference level to bring said levels back to parity conditions;

starting from a programming level of said cell to be programmed lower than said reference level, a writing operation of said first logic value involves an increase in said programming level of said cell to be programmed which brings said levels back to parity conditions, while a writing operation of said second logic value “1” involves a double increase in said programming level of said cell to be programmed to bring said programming level above said reference level.

19. The programming method according to claim 17 , further comprising: erasing said memory cell and resetting updated data only when said highest possible value is reached.

20. The programming method according to claim 17 , wherein said highest possible value is equal to the number of levels in said plurality of levels less 1.

21. A programming method for a multilevel memory cell able to store a plurality of bits in a plurality of levels, the method comprising:

writing a logic value in said multilevel memory cell by setting a programming level of the cell at one of said plurality of levels with respect to a reference level based on a symbol to be written and on a previous programming level, wherein said writing step is repeated until a highest possible value for said levels is reached; and

erasing said memory cell and resetting updated data only when said highest possible value is reached.

22. The programming method according to claim 21 , wherein said programming level of said cell to be programmed is set according to the following relation:

when writing a first logic value, said programming level of said cell is set equal to the reference level;

when writing a second logic value, said programming level of said cell is set greater than said reference level, wherein said programming level of said cell to be programmed is set according to the following relation:

starting from equal levels of the programming level and the reference level, a writing operation of said first logic value does not involve any increase in said programming level and of said reference level, while writing said second logic value involves an increase in said programming level of said cell to be programmed;

starting from a programming level of said cell to be programmed higher than said reference level, a writing operation of said second logic value does not involve any increase in said programming level and in said reference level, while a writing operation of said first logic value involves an increase in said reference level to bring said levels back to parity conditions;

starting from a programming level of said cell to be programmed lower than said reference level, a writing operation of said first logic value involves an increase in said programming level of said cell to be programmed which brings said levels back to parity conditions, while a writing operation of said second logic value “1” involves a double increase in said programming level of said cell to be programmed to bring said programming level above said reference level.

23. The programming method according to claim 21 , wherein said highest possible value is equal to the number of levels in said plurality of levels less 1.

24. A programming method for a multilevel memory cell able to store a plurality of bits in a plurality of levels, the method comprising: writing a logic value in said multilevel memory cell by setting a programming level of the cell at one of said plurality of levels with respect to a reference level based on a symbol to be written and on a previous programming level, wherein said writing step is repeated until a highest possible value for said levels is reached, wherein said highest possible value is equal to the number of levels in said plurality of levels less 1.

25. The programming method according to claim 24 , wherein said programming level of said cell to be programmed is set according to the following relation:

when writing a first logic value, said programming level of said cell is set equal to the reference level;

when writing a second logic value, said programming level of said cell is set greater than said reference level, wherein said programming level of said cell to be programmed is set according to the following relation:

starting from equal levels of the programming level and the reference level, a writing operation of said first logic value does not involve any increase in said programming level and of said reference level, while writing said second logic value involves an increase in said programming level of said cell to be programmed;

starting from a programming level of said cell to be programmed higher than said reference level, a writing operation of said second logic value does not involve any increase in said programming level and in said reference level, while a writing operation of said first logic value involves an increase in said reference level to bring said levels back to panty conditions;

starting from a programming level of said cell to be programmed lower than said reference level, a writing operation of said first logic value involves an increase in said programming level of said cell to be programmed which brings said levels back to parity conditions, while a writing operation of said second logic value “1” involves a double increase in said programming level of said cell to be programmed to bring said programming level above said reference level.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2014
From: STMICROELECTRONICS S.R.L.
To: STMICROELECTRONICS NV
Reel/Frame 032146/0367 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2014
From: STMICROELECTRONICS NV
To: NUMONYX BV
Reel/Frame 032148/0068 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2011
From: NUMONYX B.V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 027075/0682 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2003
From: DE SANDRE, GUIDO; POLES, MARCO; IEZZI, DAVID; PASOTTI, MARCO
To: STMICROELECTRONICS S.R.L.
Reel/Frame 013999/0704 →
Priority Claims (1)
EP 01830827 · Dec 28, 2001 · regional
Continuity (1)
Related Publication 20030159014A1 · Aug 21, 2003