Method of fabricating known good dies from packaged integrated circuits
View Patent ↗A known good die is economically fabricated. A tested integrated circuit is provided which includes a die having a bonding location on an upper surface and a lead. An upper portion of the integrated circuit package is removed or ground away to expose the bonding location. The lead is removed leaving the die and exposed bonding location to provide a known good die. The backside portion of the integrated circuit package is removed or ground away to expose the backside of the die. A contact pad is disposed on the bonding location. The bonding wire and exterior lead are also removed or ground away. The upper portion of the bonding ball is removed to provide a flattened bonding location. Preferably, the tested integrated circuit package provided is a thin small outline integrated circuit package (TSOP), and advantageously may be a packaged flash memory integrated circuit.
1. A method for fabricating a known good die comprising:
providing a tested integrated circuit package including a die having at least one contact pad disposed on an upper surface of the die, a corresponding bond ball connected to the contact pad, and a corresponding lead connected to the bond ball, wherein the die, the bond ball and the lead are encapsulated within packaging material with the lead extending out through the packaging material;
removing an upper portion of the packaging material to expose the bond ball, wherein the remainder of the upper surface of the die is covered by the packaging material; and
removing the lead and a portion of the packaging material containing the lead.
2. The method for fabricating a known good die according to claim 1 , wherein the fabrication process further comprises removing a lower portion of the packaging material to expose a backside of the die.
3. The method for fabricating a known good die according to claim 1 , wherein the fabrication process further comprises removing an upper portion of the bond ball to provide a flattened bonding location.
4. The method for fabricating a known good die according to claim 3 , wherein the fabrication process further comprises disposing a contact pad on the flattened bonding location.
5. The method for fabricating a known good die according to claim 4 , wherein the contact pad on the flattened bonding location is disposed lithographically.
6. The method for fabricating a known good die according to claim 4 , wherein the contact pad on the flattened bonding location is partially disposed on the packaging material.
7. The method for fabricating a known good die according to claim 1 , wherein the tested integrated circuit package comprises a thin small outline integrated circuit package (TSOP).
8. The method for fabricating a known good die according to claim 1 , wherein the tested integrated circuit package comprises a packaged flash memory integrated circuit.
9. The method for fabricating a known good die according to claim 1 , wherein the tested integrated circuit package comprises a thin small outline packaged (TSOP) flash memory integrated circuit.
10. The method for fabricating a known good die according to claim 1 , wherein the bond ball and the lead are connected using a bonding wire, and wherein the bonding wire and the packaging material containing the bonding wire are removed from the integrated circuit package.
11. The method for fabricating a known good die according to claim 1 , wherein the lead and the portion of the packaging material containing the lead are removed by dicing the integrated circuit package, and wherein a layer of packaging material is left on the lateral surfaces of the die.
12. The method for fabricating a known good die according to claim 1 , wherein the packaging material is removed from the integrated circuit package by grinding the packaging material.