Memory device having A P+ gate and thin bottom oxide and method of erasing same
View Patent ↗A non-volatile memory device includes a semiconductor substrate and an N-type source and drain within the substrate. An oxide-nitride-oxide (ONO) stack is formed over the substrate. The ONO stack includes a thin bottom oxide layer. A P + polysilicon electrode is formed over the ONO stack. The memory device is operative to perform a channel erase operation in which a pair of charge storing cells with the nitride layer are erased simultaneously.
1. A method of performing an erase operation on a non-volatile memory cell having a N + source and an N + drain within a substrate, a bottom oxide layer on a top surface of the substrate, a charge storing layer on the bottom oxide layer, a top oxide layer on the charge storing layer, and a P + polysilicon gate electrode on the top oxide, the memory device having been programmed by storing charge in a portion of the charge storing layer adjacent the source, the method comprising the simultaneous steps of:
applying a negative erase voltage to the gate electrode;
one of (i) connecting the drain to a zero potential, and (ii) floating the drain;
one of (i) connecting the source to a zero potential and (ii) floating the source; and
connecting the substrate to a zero potential.
2. The method according to claim 1 , wherein the simultaneous steps occur for a duration of at least about 100 ms.
3. The method according to claim 2 , wherein the erase voltage applied to the gate is in a range of about −10 volts to about −20 volts.
4. The method according to claim 2 , wherein the erase voltage applied to the gate is less than about −20 volts.
5. The method according to claim 2 , wherein the duration is less than about 1 sec.
6. The method according to claim 1 , wherein the charge storing layer includes two bits, both bits being erased simultaneously.
7. A method of simultaneously erasing two charge storing cells on a non-volatile memory device having an N + source and an N + drain within a P-type substrate, an oxide-nitride-oxide (ONO) stack on a top surface of the substrate, said charge storing cells being disposed within the nitride layer of the ONO stack, and a gate layer on the ONO stack, said method comprising:
increasing a potential barrier height of the top oxide of the ONO stack, said increased potential barrier height being effective to decrease the probability that, during an erase operation, electrons within the gate layer will overcome a potential barrier of the top oxide and become trapped in the charge storing cells of the nitride layer;
decreasing a barrier width of the bottom oxide of the ONO stack, said decreased barrier width being effective to (i) increase the probability that, during an erase operation, electrons within the charge storing cells of the nitride layer will overcome a potential barrier of the bottom oxide to exit the charge storing cells, and (ii) decrease the probability that, during operations other than an erase operation, charge will overcome a potential barrier of the bottom oxide and escape from the charge storing cells;
applying a negative erase voltage of less than about −20 volts to the gate layer;
one of (i) applying a zero potential to the source, and (ii) floating the source;
one of (i) applying a zero potential to the drain, and (ii) floating the drain; and
applying a zero potential to the substrate.
8. The method according to claim 7 , wherein increasing the potential barrier height includes:
heavily doping the gate layer to provide P + conductivity.
9. The method according to claim 8 , wherein decreasing the barrier width includes:
decreasing the thickness of the bottom oxide layer to between about 40 Å and about 60 Å.