Leadless plastic chip carrier with etch back pad singulation
View Patent ↗A leadless plastic chip carrier is constructed by half etching one or both sides of the package design onto a leadframe strip so as to create unique design features such as power and/or ground ring surrounding the die attach pad, interlocking rivet head construction for the contact pads, and an interlocking pattern for the die attach pad. After wire bonding and molding, a further etching is performed to isolate and expose contact pads. Singulation of individual chip packages from the leadframe strip is then performed by saw singulation or die punching.
1. A process for fabricating a leadless plastic chip carrier, comprising the steps of:
depositing a mask on a first surface of a leadframe strip to define at least one row of contact pads and a power/ground ring adjacent a die attach pad of said leadless plastic chip carrier;
depositing a plurality of layers on portions of said surface exposed by said mask for creating said at least one row of contact pads, said power/ground ring and said die attach pad;
dissolving away said mask;
mounting a semiconductor die to said die attach pad on said top surface and wire bonding said semiconductor die to said contact pads;
encapsulating said top surface of said leadframe strip in a molding material;
etching back a bottom surface of said leadframe strip for exposing said contact pads and said die attach pad; and
singulating said leadless plastic chip carrier from said leadframe strip.
2. The process of claim 1 , wherein said step of depositing said plurality of layers includes an initial deposition of flash Cu which is etched away during step of etching back said bottom surface to create a cavity, and further including a step of attaching solder balls to said contact pads exposed as a result of said step of etching back said bottom surface of said leadframe strip.
3. The process of claim 2 , wherein said initial deposition of flash Cu is followed by depositing layers of Au, Ni, Cu, Ni and Au.
4. The process of claim 2 , wherein said initial deposition of flash Cu is followed by depositing layers of Au, Ni, Cu and Ag.
5. The process of claim 1 , wherein said step of depositing said plurality of layers includes depositing successive layers of Au, Ni, Cu, Ni and Au.
6. The process of claim 1 , wherein said step of depositing said plurality of layers includes depositing successive layers of Au, Ni, Cu, and Ag.
7. The process of claim 1 , wherein said step of depositing said plurality of layers includes depositing successive layers of Tin, Cu, Ni and Au.
8. The process of claim 1 , wherein said step of depositing said plurality of layers includes depositing successive layers of Tin, Cu, and Ag.