Direct memory access controller, direct memory access device, and request device

1. A direct memory access controller, comprising:

one request signal input terminal inputting data transfer request signals from a plurality of request devices;

one acknowledge signal output terminal outputting an acknowledge signal to said plurality of request devices; and

a control circuit controlling a data transfer based on the request signal from one of said plurality of request devices in response to the request signal inputted from said request signal input terminal, wherein

said control circuit outputs the acknowledge signal from said acknowledge signal output terminal, and thereafter controls a data transfer based on the request signal from one of said plurality of request devices in response to a timing when the request signal inputted from said request signal input terminal changes in level.

2. The direct memory access controller according to claim 1 , wherein

said control circuit controls a data transfer between memories.

3. The direct memory access controller according to claim 1 , wherein

said control circuit controls a data transfer between an input and/or output device and a memory.

4. The direct memory access controller according to claim 1 , wherein

said control circuit outputs the acknowledge signal from said acknowledge signal output terminal when the request signal is inputted from said request signal input terminal, and thereafter controls a data transfer based on the request signal from one of said plurality of request devices in response to a timing when the input of the request signal is completed.

5. The direct memory access controller according to claim 4 , wherein

said control circuit stores a relationship between said plurality of request devices and the input completion timing of the request signal.

6. The direct memory access controller according to claim 5 , wherein

said control circuit outputs the acknowledge signal in pulse form from said acknowledge signal output terminal.

7. The direct memory access controller according to claim 1 , wherein

said control circuit outputs the acknowledge signal from said acknowledge signal output terminal when the request signal is inputted from said request signal input terminal, and thereafter controls a data transfer based on the request signal from one of said plurality of request devices in response to a timing when the input of the request signal is completed and then input of the request signal is again started.

8. The direct memory access controller according to claim 7 , wherein

said control circuit stores a relationship between said plurality of request devices and the input start timing of the request signal.

9. The direct memory access controller according to claim 8 , wherein

said control circuit outputs the acknowledge signal in pulse form from said acknowledge signal output terminal.

10. A direct memory access device to which a direct memory access controller and a plurality of request devices are connected, wherein said direct memory access controller comprises:

one request signal input terminal inputting a request signal while at least one of said plurality of request devices is outputting the request signal;

one acknowledge signal output terminal outputting an acknowledge signal to said plurality of request devices; and

a control circuit outputting the acknowledge signal from said acknowledge signal output terminal, and thereafter controlling a data transfer based on the request signal from one of said plurality of request devices in response to a timing when the request signal inputted from said request signal input terminal changes in level, wherein each of said request devices comprises

a request signal input/output terminal outputting the request signal and inputting the request signal while at least one of said plurality of request devices is outputting the request signal,

an acknowledge signal input terminal inputting the acknowledge signal outputted from said direct memory access controller, and

a control circuit inputting the acknowledge signal from said acknowledge signal input terminal, and thereafter changing a level of the request signal outputted to said request signal input/output terminal after a lapse of a fixed period which is different for each of said request devices to make a request for a data transfer.

11. The direct memory access device according to claim 10 , wherein

said control circuit of said direct memory access controller outputs the acknowledge signal from said acknowledge signal output terminal when the request signal is inputted from said request signal input terminal, and thereafter controls a data transfer based on the request signal from one of said plurality of request devices in response to a timing when the input of the request signal is completed.

12. The direct memory access device according to claim 10 , wherein

said control circuit of said direct memory access controller outputs the acknowledge signal from said acknowledge signal output terminal when the request signal is inputted from said request signal input terminal, and thereafter controls a data transfer based on the request signal from one of said plurality of request devices in response to a timing when the input of the request signal is completed and then input of the request signal is again started.

13. A request device, comprising:

a request signal input/output terminal outputting a request signal and inputting the request signal on a request signal line;

an acknowledge signal input terminal inputting an acknowledge signal; and

a control circuit inputting the acknowledge signal from said acknowledge signal input terminal, and thereafter changing a level of the request signal to be outputted to said request signal input/output terminal after a lapse of a fixed period to make a request for direct memory access.

14. The request device according to claim 13 , wherein

said control circuit outputs the request signal from said request signal input/output terminal, thereafter inputs the acknowledge signal from said acknowledge signal input terminal, and then completes the output of the request signal after a lapse of a fixed period to make a request for direct memory access.

15. The request device according to claim 14 , wherein

said control circuit determines acceptance or rejection of the request in accordance with whether or not said request signal line changes in level at a timing of completion of the output of the request signal.

16. The request device according to claim 13 , wherein

said control circuit outputs the request signal from said request signal input/output terminal, thereafter inputs the acknowledge signal from said acknowledge signal input terminal, and then completes the output of the request signal and starts output of the request signal after a lapse of a fixed period to thereby-make a request for direct memory access.

17. The request device according to claim 16 , wherein

said control circuit determines acceptance or rejection of the request in accordance with whether or not said request signal line changes in level at a timing of the start of the output of the request signal.