Threshold voltage adjustment method of non-volatile semiconductor memory device and non-volatile semiconductor memory device
View Patent ↗It is intended to provide a nonvolatile semiconductor memory device which maintains the maximum number of over-erase memory cells which are conductive when adjusting the threshold voltage after data erase by controlling the gate voltage of a memory cell continuously in order to adjust the threshold voltage in a short time and a nonvolatile voltage adjustment method. There is formed a feedback loop for controlling the number of memory cells to be conductive in a memory cell group by controlling a gate voltage generating circuit through a differential amplifier from a drain terminal and the gate voltage generating circuit is controlled by the differential amplifier so as to maintain the drain voltage at a predetermined drain voltage VRF. A variable gate voltage can be controlled continuously by a feedback loop for controlling the variable gate voltage based on a difference voltage between the drain voltage and the predetermined drain voltage. Thus, effective threshold voltage adjustment operation is enabled corresponding to a current supply capacity regardless of the current supply capacity of the drain voltage generating circuit.
1. A threshold voltage adjustment method of a non-volatile semiconductor memory device that has memory cells and conducts data erase of the memory cells by changing threshold voltage with electrical bias, the threshold voltage adjustment method adjusting the threshold voltage to the memory cells after the data erase and comprising steps of:
drain voltage applying step for applying drain voltage to drain terminals of the memory cells;
comparing step for comparing the drain voltage to be applied to the drain terminals with predetermined drain voltage; and
gate voltage applying step for controlling the drain voltage applying step by applying variable gate voltage to gate terminals of the memory cells in accordance with a comparison result obtained in the comparing step.
2. A threshold voltage adjustment method of a non-volatile semiconductor memory device according to claim 1 , wherein the variable gate voltage continuously varies in the gate voltage applying step so as to keep the drain voltage to the predetermined drain voltage in the drain voltage applying step.
3. A threshold voltage adjustment method of a non-volatile semiconductor memory device according to claim 2 , wherein, in the gate voltage applying step, the variable gate voltage is controlled depending on difference voltage of the drain voltage obtained with reference to the predetermined drain voltage at the comparing step.
4. A threshold voltage adjustment method of a non-volatile semiconductor memory device according to claim 3 , wherein the variable gate voltage is raised in response to the difference voltage in positive and is lowered in response to the difference voltage in negative.
5. A threshold voltage adjustment method of a non-volatile semiconductor memory device according to claim 1 , wherein the variable gate voltage is continuously raised from initial voltage toward final voltage.
6. A threshold voltage adjustment method of a non-volatile semiconductor memory device according to claim 1 , wherein initial voltage of the variable gate voltage is negative voltage with reference to applied voltage to source terminals of the memory cells.
7. A threshold voltage adjustment method of a non-volatile semiconductor memory device according to claim 1 , wherein final voltage of the variable gate voltage is equivalent to predetermined gate voltage that is same as or lower than maximum threshold voltage among the memory cells in condition of the data erase.
8. A threshold voltage adjustment method of a non-volatile semiconductor memory device according to claim 1 further comprising adjustment-operation-stop instructing step for instructing to stop adjustment of the threshold voltage by constantly monitoring the variable gate voltage and detecting that the variable gate voltage reaches predetermined gate voltage.
9. A threshold voltage adjustment method of a non-volatile semiconductor memory device according to claim 8 further comprising detection voltage adjusting step for varying the predetermined gate voltage.
10. A threshold voltage adjustment method of a non-volatile semiconductor memory device according to claim 1 , wherein the predetermined drain voltage is boosted voltage.
11. A threshold voltage adjustment method of a non-volatile semiconductor memory device according to claim 1 , wherein batch adjustment of the threshold voltage is conducted to an erased region where the data erase in memory cell array is conducted.
12. A threshold voltage adjustment method of a non-volatile semiconductor memory device according to claim 1 , batch adjustment of the threshold voltage is conducted to predetermined number of bit lines out of a plurality of bit lines included in an erase region to which the data erase in memory cell array is conducted.
13. A non-volatile semiconductor memory device conducting data erase of memory cells by changing threshold voltage with electrical bias, for adjusting the threshold voltage of the memory cells after the data erase, the non-volatile semiconductor memory device comprising:
a drain voltage generating section for supplying drain voltage to drain terminals of the memory cells, the drain voltage generating section being activated based on a threshold voltage adjusting signal;
a drain voltage detecting section for detecting the drain voltage; and
a gate voltage generating section for controlling variable gate voltage to be applied to gate terminals of the memory cells based on a drain voltage detecting signal from the drain voltage detecting section, the gate voltage generating section being activated based on the threshold voltage detecting signal.
14. A non-volatile semiconductor memory device according to claim 13 , wherein the variable gate voltage is continuously varied in the gate voltage generating section so as to keep the drain voltage to predetermined drain voltage.
15. A non-volatile semiconductor memory device according to claim 13 , wherein the drain voltage detecting section includes a differential amplifier that outputs the drain voltage detecting signal in accordance with a reference input signal inputted based on the predetermined drain voltage and an input signal inputted based on the drain voltage.
16. A non-volatile semiconductor memory device according to claim 13 , wherein the gate voltage generating section includes a voltage adjusting section controlled by the drain voltage detecting signal, and the voltage adjusting section conducts: positive voltage adjustment to the drain voltage detecting signal that indicates the drain voltage is higher than the predetermined drain voltage; and negative voltage adjustment to the drain voltage detecting signal that indicates the drain voltage is lower than the predetermined drain voltage.
17. A non-volatile semiconductor memory device according to claim 13 further comprising a gate voltage detecting section for detecting the variable gate voltage as predetermined gate voltage, wherein at least either one of the drain voltage generating section or the gate voltage generating section is deactivated based on a gate voltage detecting signal from the gate voltage detecting section.
18. Anon-volatile semiconductor memory device according to claim 17 , wherein the gate voltage detecting section includes a predetermined gate voltage setting section for setting the predetermined gate voltage.
19. Anon-volatile semiconductor memory device according to claim 13 , wherein in case the data erase is conducted by selecting at least one sector plotted for each predetermined region of memory cell array as erase sector, the non-volatile semiconductor memory device further includes a sector gate section for connecting at least either one of the drain voltage generating section or the gate voltage generating section to the erase sector, and batch adjustment of the threshold voltage is conducted to the erase sector.
20. A non-volatile semiconductor memory device according to claim 13 further comprising a path gate section for connection at least either one of the drain voltage generating section or the gate voltage generating section to predetermined number of bit lines out of a plurality of bit lines included in an erase sector to which the data erase is conducted, and batch adjustment of the threshold voltage to the predetermined number of bit lines is conducted.