Granted Patent B2

US 6,933,610 · App. 10/370,422 · Granted Aug 23, 2005

Abstract

Claims (47)

1. A method of bonding a semiconductor die without an ESD circuit and a separate ESD circuit to an external lead, said method comprising:

bonding said external lead to said separate ESD circuit;

then bonding said separate ESD circuit to said semiconductor die;

packaging said die and said circuit in a single package, wherein said external lead is bonded to said ESD circuit and to said semiconductor die

coupling the package to a chip carrier, said carrier having a first surface having said external lead, and a second surface opposite said first surface and an aperture between said first surface and said second surface

said semiconductor die having a mounting surface with a mounting pad thereon;

said mounting surface facing said second surface with said mounting pad in said aperture;

said ESD circuit on said mounting surface in said aperture;

wherein said external lead is bonded to said ESD circuit in said aperture and to said mounting pad in said aperture; and

wherein said semiconductor die is a memory die, said die being substantially rectilinear in share with a plurality of rows having a plurality of mounting pads thereon substantially in the middle of said rectilinear shape.

2. The method of claim 1 , wherein a plurality of ESD circuits are mounted on a strip.

3. The method of claim 2 further comprising mounting said strip of ESD circuits to said mounting surface of said semiconductor die, adjacent to said plurality of mounting pads prior to bonding an external lead to one of said ESD circuits.

4. A semiconductor device comprising:

a chip carrier having a first surface having a plurality of leads, and a second surface opposite said first surface and an aperture between said first surface and said second surface;

a semiconductor die having a mounting surface with a mounting pad thereon, wherein said die is substantially rectilinearly shaped with a plurality of rows of mounting pads substantially in the middle of said die;

said mounting surface facing said second surface with said mounting pad in said aperture;

an ESD circuit on said mounting surface in said aperture;

a first electrical connector connecting one of said plurality of leads to said ESD circuit; and

a second electrical connector connecting said ESD circuit to said mounting pad, wherein said first electrical connector and said second electrical connector are the same connector.

5. The semiconductor device claim 4 further comprising:

a die adhesive for attaching said semiconductor die to said chip carrier; and

a package for encapsulating said ESD circuit and said aperture.

6. The semiconductor device of claim 5 wherein said package further encapsulates said die with said chip carrier.

7. The semiconductor device of claim 4 further comprising a plurality of ESD circuits, each mounted on said mounting surface with each ESD circuit substantially adjacent to a mounting pad in said aperture.

8. A method of assembling a semiconductor device, said device including a semiconductor die having an integrated circuit with a plurality of rows of mounting pads connecting to said integrated circuit, on a mounting surface, said method comprising:

mounting a strip on said mounting surface, substantially adjacent to said plurality of rows of mounting pads, said strip having a plurality of ESD circuits;

bonding an external lead to one of said ESD circuits; and

then bonding one of said ESD circuits having said external lead bonded, to one of said mounting pads.

9. The method of claim 8 further comprising the step of:

mounting said semiconductor die on a chip carrier, said chip carrier having a first surface with a plurality of external leads, a second surface, opposite said first surface, and an aperture between said first surface and said second surface; said die mounted with said mounting surface facing said second surface and said mounting pads in said aperture.

10. The method of claim 9 wherein said semiconductor die is mounted on said chip carrier before said strip is mounted on said die.

11. The method of claim 9 wherein said semiconductor die with said strip mounted thereon is mounted on said chip carrier with said ESD circuits in said aperture.

12. The method of claim 9 wherein said external lead is bonded to one of said ESD circuits and said same external lead is bonded to one of said mounting pads.

13. The method of claim 4 wherein said integrated circuit is a circuit.

14. A semiconductor device comprising:

a semiconductor die having an input pad for receiving an input signal;

an ESD circuit electrically connected to said input pad;

a terminating resistor switchably connected to said input pad;

said ESD circuit and said resistor external to said die;

said ESD circuit, said resistor and said die packaged in a single package; and

an external lead connected to said input pad.

15. The device claim 14 wherein said resistor is switchably connected to said input pad in response to a control signal.

16. The device of claim 14 wherein said resistor is switchably connected to said input pad through a fuse.

17. The device of claim 14 wherein said terminating resistor is made of thin film.

18. The device of claim 14 wherein said semiconductor die is a memory circuit.

19. The device of claim 18 wherein said memory circuit is a DRAM, double data rate (DDR) circuit.

20. The device of claim 19 wherein said resistor is switchably connected to said input pad in response to the performance of said DDR circuit.

Assignments (7)