Low-jitter delay cell

1. A differential delay cell comprising:

a voltage bus;

a differential pair of metal-oxide-silicon (MOS) transistors having respective source terminals coupled to define a current node, and respective drain terminal outputs that cooperate to form a differential output;

a bias current source disposed at the current node; and

a differential diode-connected load disposed between the differential pair and the voltage bus, the differential diode-connected load comprising at least one n-channel MOS transistor configured as a diode.

2. The differential delay cell of claim 1 wherein the diode-connected load comprises a pair of n-channel MOS transistors.

3. The differential delay cell of claim 1 wherein the diode-connected load further includes at least one current source disposed in parallel with the at least one n-channel MOS transistor.

4. The differential delay cell of claim 3 wherein the at least one current source comprises a pair of current sources, the current sources are disposed in parallel with the at least one n-channel MOS transistor.

5. The differential delay cell of claim 1 wherein the differential diode-connected load further comprises a p-channel MOS transistor disposed in parallel with the at least one n-channel MOS transistor.

6. The differential delay cell of claim 1 wherein the bias current source comprises a cascoded current source.

7. A timing generator for use in a semiconductor tester, the timing generator comprising:

a delay line having a plurality of delay cells with respective phase-shifted outputs, the delay cells comprising:

a voltage bus;

a differential pair of metal-oxide-silicon (MOS) transistors having respective source terminals coupled to define a current node, and respective drain terminal outputs that cooperate to form a differential output;

a current source disposed at the current node; and

a differential diode-connected load disposed between the differential pair and the voltage bus, the differential diode-connected load comprising at least one n-channel MOS transistor configured as a diode;

a multiplexer having a plurality of inputs for receiving the phase shifted outputs, and an output; and

phase detection circuitry for detecting the phase shift between the multiplexer output and a reference signal.

8. The timing generator of claim 7 wherein the diode-connected load comprises a pair of n-channel MOS transistors.

9. A The timing generator of claim 7 wherein the diode-connected load further includes at least one current source disposed in parallel with the at least one n-channel MOS transistor.

10. The timing generator of claim 9 wherein the at least one current source comprises a pair of current sources, the current sources disposed in parallel with the at least one n-channel MOS transistor.

11. The timing generator of claim 7 wherein the differential diode-connected load further comprises a p-channel MOS transistor disposed in parallel with the at least one n-channel MOS transistor.

12. The timing generator of claim 7 wherein the bias current source comprises a cascoded current source.

13. A method comprising:

delaying a timing signal through a delay cell, the delay cell including a voltage supply bus for providing a bias voltage, delaying comprising:

generating a bias current in the delay cell, the bias current controlling the amount of delay provided by the delay cell;

detecting the timing signal; and

establishing a negative-feedback path to compensate for voltage variations on the voltage supply bus using a differential diode comprising an n-channel MOS transistor in a diode configuration.

14. The method of claim 13 , wherein detecting the timing signal comprises detecting the timing signal using a differential switch comprising a differential pair of metal-oxide-silicon (MOS) transistors.

15. The method of claim 14 wherein establishing a negative-feedback path comprises connecting a differential diode-connected load between the bus and the differential switch.

16. A method comprising:

compensating for delay based on variations to a bias voltage acting on a bias current of a differential delay cell, the differential delay cell having a differential diode-connected load comprising an n-channel MOS transistor in a diode configuration, compensating comprising establishing a first bias current through the differential delay cell to achieve a desired delay characteristic for the differential delay cell.

17. The method of claim 16 , further comprising detecting changes to the bias voltage.

18. The method of claim 17 , further comprising compensating for effects on the bias current based on the changes to the bias voltage.