Semiconductor memory device with test mode and testing method thereof
View Patent ↗A synchronous SRAM includes a register sequentially providing data signals of the burst length in a test mode, and a transfer circuit applying data signals output from the register to a memory array for burst-writing, and providing to an external source via an IO buffer a data signal read out in a burst manner later than the burst writing by 1 clock cycle. It is not necessary to additionally apply a data signal for writing. The required number of address signals can be reduced. Thus, testing can be simplified.
1. A semiconductor memory device operating in synchronization with a clock signal, comprising:
a plurality of memory cells;
a register sequentially providing one by one N (N is an integer of at least 2) data signals written in advance in a test mode testing whether each memory cell is proper or not;
a decoder sequentially selecting one by one N memory cells from said plurality of memory cells according to an address signal;
a write circuit sequentially writing the N data signals output from said register into the N memory cells selected by said decoder; and
a read circuit operating later than said write circuit by M (M is an integer of at least 1 and not more than N−1) clock cycles, and sequentially reading out data signals from the N memory cells selected by said decoder.
2. The semiconductor memory device according to claim 1 , wherein said decoder comprises a burst counter sequentially incrementing said address signal in synchronization with said clock signal to further generate N−1 address signals.
3. The semiconductor memory device according to claim 1 , wherein said plurality of memory cells are divided into N memory blocks, each including a plurality of memory cells,
wherein said decoder sequentially selects one by one N memory cells from said N memory blocks respectively according to said address signal.
4. The semiconductor memory device according to claim 1 , wherein a plurality of registers are provided,
said semiconductor memory device further comprising a select circuit selecting any of said plurality of registers according to a select signal to provide a data signal output from the selected register to said write circuit.
5. A method of testing the semiconductor memory device defined in claim 1 , comprising the steps of:
rendering said semiconductor memory device active to set said semiconductor memory device at a test mode;
applying said address signal to said decoder; and
determining whether each memory cell is proper or not based on a data signal read out by said read circuit.