Granted Patent B2

US 6,897,684 · App. 10/379,200 · Granted May 24, 2005

Abstract

Claims (29)

1. An input buffer circuit comprising:

a differential amplifier that receives an input signal and a reference voltage for determining the level of the input signal;

a first operating current path transistor for supplying a prescribed first operating current to said differential amplifier, said first operating current path transistor, by being supplied at its gate with a prescribed fixed voltage, always being in the on state; and

a second operating current path transistor for supplying a second operating current that is greater than said first operating current to said differential amplifier when on, said second operating current path transistor being on/off-controlled in accordance with a control signal from the outside,

said first operating current path transistor and said second operating current path transistor being connected directly to said differential amplifier.

2. The input buffer circuit according to claim 1 , wherein channel resistance of said second operating current path transistor is less than that of said first operating current path transistor.

3. A semiconductor memory device that requires a refresh operation for holding data that have been written in memory cells, said semiconductor memory device comprising:

an input buffer circuit according to claim 2 for receiving a clock enable signal that is supplied from the outside for setting said semiconductor memory device in said refresh operation state; and

a control circuit for generating, in accordance with an output signal of said input buffer circuit, a refresh operation signal that indicates whether or not said semiconductor memory device is in the refresh operation state, and supplying the refresh operation signal to said input buffer circuit as said control signal.

4. The input buffer circuit according to claim 1 , wherein said differential amplifier comprises:

a first transistor and a second transistor that are formed from p-channel MOSFETs and that form a current mirror circuit;

a third transistor for receiving said input signal at its gate, said third transistor being formed from an n-channel MOSFET and being connected in a series with said first transistor; and

a fourth transistor for receiving said reference voltage at its gate, said fourth transistor being formed from an n-channel MOSFET, having its source connected in common with the source of said third transistor, and being connected in a series with said second transistor;

wherein said first operating current path transistor and said second operating current path transistor are each fornied from n-channel MOSFETs.

5. A semiconductor memory device that requires a refresh operation for holding data that have been written in memory cells, said semiconductor memory device comprising:

an input buffer circuit according to claim 4 for receiving a clock enable signal that is supplied from the outside for setting said semiconductor memory device in said refresh operation state; and

a control circuit for generating, in accordance with an output signal of said input buffer circuit, a refresh operation signal that indicates whether or not said semiconductor memory device is in the refresh operation state, and supplying the refresh operation signal to said input buffer circuit as said control signal.

6. The input buffer circuit according to claim 1 , wherein said differential amplifier comprises:

a first transistor and a second transistor that are formed from n-channel MOSFETs and that form a current mirror circuit;

a third transistor for receiving said input signal at its gate, said third transistor being formed from a p-channel MOSFET and being connected in a series with said first transistor; and

a fourth transistor for receiving said reference voltage at its gate, said fourth transistor being formed from a p-channel MOSFET, having its source connected in common with the source of said third transistor, and being connected in a series with said second transistor;

wherein said first operating current path transistor and said second operating current path transistor are each formed from p-channel MOSFETS.

7. A semiconductor memory device that requires a refresh operation for holding data that have been written in memory cells, said semiconductor memory device comprising:

an input buffer circuit according to claim 6 for receiving a clock enable signal that is supplied from the outside for setting said semiconductor memory device in said refresh operation state;

a control circuit for supplying as output, in accordance with an output signal of said input buffer circuit, a refresh operation signal that indicates whether or not said semiconductor memory device is in the refresh operation state; and

an inverter for inverting said refresh operation signal that is supplied as output from said control circuit and supplying the inverted signal as said control signal to said input buffer circuit.

8. A semiconductor memory device that requires a refresh operation for holding data that have been written in memory cells, said semiconductor memory device comprising:

an input buffer circuit according to claim 1 for receiving a clock enable signal that is supplied from the outside for setting said semiconductor memory device in said refresh operation state; and

a control circuit for generating, in accordance with an output signal of said input buffer circuit, a refresh operation signal that indicates whether or not said semiconductor memory device is in the refresh operation state, and supplying the refresh operation signal to said input buffer circuit as said control signal.

Assignments (8)