Processor bus arrangement
View Patent ↗A processor bus has several data processing units, each connected to a line system which acts as a bus having bus segments connected in a separable manner through connection units. Functional units arranged on the bus carry out the information thereof. The functional units may carry out exchanges independently of each other. Conversely, functional units in different groups may carry out information exchanges simultaneously. The connection units define combinatory connections of the signal lines, with physical connections between the connection units provided by the bus segments. The connection units can carry out information exchanges with as many connected functional units as desired. The information path from a functional unit to selected functional units can be multiplexed or switched by toggling simultaneous connections to several functional units or by bridging non-participating functional units.
1. A processor bus arrangement in a single chip vector processor, comprising:
at least a first and a second data processing units internal to the single chip vector processor, each of which is connected to a system of lines combined as a bus internal to the vector processor,
wherein the bus has connection units and bus segments, wherein the bus segments provide line connections to and between the connection units of the vector processor,
wherein the bus segments are connected to the bus in a separable manner by means of the connection units so that each bus segment operates as a bus between interconnected data processing units of the vector processor even when isolated from the remaining bus and bus segments,
wherein the bus has multiple paths, which unidirectional or bidirectionally perform data transmission, are arranged in the connection unit,
wherein a second and a third connection unit are arranged in a chain with a first connection unit as a repeater structure, wherein the connection units of the repeater structure are arranged chained together in one of a star and a ring, and wherein the connection units are arranged to bridge across adjacent connection units.
2. The processor bus arrangement according to claim 1 , wherein a termination unit is arranged at each end of the chained repeater structure of said connection units.
3. The processor bus arrangement according to claim 2 , wherein a termination unit is switched onto the repeater structure as a terminator without additional connection.
4. The processor bus arrangement according to claim 2 , wherein a termination unit is directly connected to connection units.
5. The processor bus arrangement according to claim 1 , wherein the connection unit comprises a multiplexer.
6. The processor bus arrangement according to claim 5 , wherein the multiplexer gate function is expanded to the logical operations OR and XOR.
7. The processor bus arrangement according to claim 5 , wherein the multiplexer is a bidirectional multiplexer wherein;
an ICU_IN_RIGHT signal line is connected to a first input of a first input signal amplifier and simultaneously to a first input of a first output gate, whose output is connected to the ICU_Out_Right signal line;
the output of the first input signal amplifier is connected to a first input of a second output gate and simultaneously to a first input of a third output gate,
a second input is connected to the MEM_In_SLC1_Right signal line and simultaneously to a first input of a first logic gate and wherein the output is connected the second input of the first output gate;
the output of the second output gate is connected to a signal line MEM_Out_SLC1_Right and the input of the second output gate is connected to a signal line RFU_In_Slc1_Right and simultaneously to the second input of the first logic gate,
the output of the third output gate is connected to an RFU_Out_Slc1_Right signal line, wherein an ICU_IN_Left signal line is connected to an input of a second input signal amplifier and simultaneously to a first input of a fourth output gate and its output is connected to an ICU_Out_Left signal line;
the output of the second input signal amplifier is connected to a first input of a fifth output gate and simultaneously to a first input of sixth output gate whose second input is connected to the MEM_In_SL1_Left signal line and simultaneously to a first input of a second logic gate and whose output is connected to the second input of the fourth output gate;
the output of the fifth output gate is connected to a signal line MEM_Out_SLC1_Left and the second input of a fifth output gate is connected to a signal line RFU_In_Slc1_Left and simultaneously to the second input of the second logic gate;
the output of the sixth output gate is connected to an RFU_Out_Slc1_Left signal line;
a signal line RFU_In_Slc0_Right is connected to a signal line MEM_Out_Slc0_Right;
a signal line RFU_Out_Slc0_Right is connected to a signal line MEM_In_Slc0_Right;
a signal line RFU_In_Slc0_Left is connected to a signal line MEM_Out_Slc0_Left; and
a signal line RFU_Out_Slc0_Left is connected to a signal line MEM_Out_Slc0_Left.
8. The processor bus arrangement according to claim 5 , wherein the multiplexer is a dual slice bidirectional multiplexer wherein;
an ICU_IN_RIGHT signal line is connected to a first input of a third input signal amplifier and simultaneously to a first input of a seventh output gate and whose output is connected to the ICU_Out_Right signal line;
the output of the third input signal amplifier is connected to a first input of an eighth output gate and simultaneously to a first input of a ninth output gate as well as to a first input of a third logic gate;
the second input of the ninth output gate is connected to the MEM_In_SL1_Right signal line and simultaneously to the second input of the third logic gate as well as a first input of a fourth logic gate and whose output is connected to a first input of a fifth logic gate;
the output of the eighth output gate is connected to a signal line MEM_Out_SLC1_Right and its second input is connected in turn to a signal line RFU_In_Slc1_Right and simultaneously to the third input of the third logic gate and the second input of the fourth logic gate;
the output of the ninth output gate is connected to an RFU_Out_Slc1_Right signal line;
the output of the third logic gate is connected to a first input of a fifteenth output gate and simultaneously to a first input of a sixteenth output gate whose output is in turn connected to the RFU_Out_Slc0_Right signal line;
the RFU_In_Slc0_Right signal line is connected to the second input of the fifteenth output gate and also to a first input of a tenth logic gate wherein its output is connected to the second input of the fifth logic gate;
the second input of the tenth logic gate is connected to the MEM_In_Slc0_Right signal line and also to the second input of the sixteenth output gate;
the output of the fifteenth output gate is connected to the MEM_Out_Slc0_Right signal line;
the output of the fifth logic gate is connected to the second input of the seventh output gate;
an ICU_IN_Left signal line is connected to a first input of a fourth input signal amplifier and simultaneously to a first input of a tenth output gate and its output is connected to the ICU_Out_Left signal line;
the output of the fourth input signal amplifier is connected to a first input of a thirteenth output gate and simultaneously to a first input of a fourteenth output gate as well as to a first input of a ninth logic gate;
the second input of the fourteenth output gate is connected to the RFU_In_SLc0_Left signal line and simultaneously to the second input of the ninth logic gate as well as to a first input of an eighth logic gate and whose output is connected to a first input of a seventh logic gate;
the output of the thirteenth output gate is connected to a signal line RFU_Out_SLC0_Left and its second input in turn is connected to a signal line MEM_In_Slc0_Left and simultaneously to the third input of the ninth logic gate and also to the second input of the eighth logic gate;
the output of the fourteenth output gate is connected to a MEM_Out_Slc0_Left signal line;
the output of the ninth logic gate is connected to a first input of an eleventh output gate and simultaneously to a first input of a twelfth output gate whose output in turn is connected to the RFU_Out_Slc1_Left signal line;
the MEM_In_Slc1_Left signal line is connected to the second input of the twelfth output gate and also to a first input of a sixth logic gate wherein its output is connected to the second input of the seventh logic gate;
the second input of the sixth logic gate is connected to the RFU_In_Slc1_Left signal line and also to the second input of the eleventh output gate whose output is connected to the MEM_Out_Slc1_Left signal line; and
the output of the seventh logic gate is connected to the second input of the seventh output gate.