Content addressable memory (CAM) devices that utilize priority class detectors to identify highest priority matches in multiple CAM arrays and methods of operating same
View Patent ↗Content addressable memory devices may include a priority encoder therein and a first tier of CAM arrays arranged side-by-side relative to each other, on a first side of the priority encoder. A priority class detector is also provided for efficiently communicating match information that is generated during a search operation. The priority class detector passes match information from a selected priority class of rows in a selected one of the CAM arrays in the first tier to the priority encoder. This operation to pass match information is performed in response to detecting a match in the selected priority class when a search operation is performed. The priority class detector performs operations to locally encode match lines associated with a respective CAM array by priority class. These match lines are associated with a plurality of consecutive rows or consecutive pairs of rows that are arranged in a repeating priority class sequence comprising different priority classes. The priority class sequence may be an alternating priority class sequence, with each physically even row (or even pair of rows) in a CAM array being associated with one priority class and each physically odd row (or odd pair of rows) in a CAM array being associated within another priority class. Alternative priority class sequences may also be provided.
1. A content addressable memory (CAM) device, comprising:
a priority encoder;
a first tier of CAM arrays arranged side-by-side relative to each other, on a first side of said priority encoder; and
a priority class detector that is configured to pass match information from a selected priority class in a selected one of the CAM arrays in said first tier to said priority encoder, in response to detecting a match in the selected priority class during a search operation.
2. The CAM device of claim 1 , wherein with respect to each of a plurality of CAM arrays in said first tier, said priority class detector is configured to locally encode match lines associated with a respective CAM array by priority class.
3. The CAM device of claim 2 , wherein a plurality of consecutive rows or consecutive pairs of rows in a CAM array within said first tier are arranged by alternating priority class.
4. The CAM device of claim 2 , wherein a plurality of consecutive rows or consecutive pairs of rows in a CAM array within said first tier are arranged in a repeating priority class sequence comprising different priority classes.
5. The CAM device of claim 1 , further comprising:
a global word line decoder; and
a plurality of global word lines that are electrically coupled to said global word line decoder and to said priority class detector.
6. The CAM device of claim 5 , wherein said priority encoder is electrically coupled to said plurality of global word lines; and wherein said priority class detector is configured to pass the match information on said plurality of global word lines.
7. The CAM device of claim 6 , wherein said priority class detector is configured to pass the match information on said plurality of global word lines as active low signals.
8. The CAM device of claim 1 , wherein the selected one of the CAM arrays is a highest priority CAM array in said first tier.
9. A content addressable memory (CAM) device, comprising:
a CAM array having N consecutive rows of CAM cells that are electrically coupled to a respective first plurality of match lines and M consecutive rows of CAM cells that are electrically coupled to a respective second plurality of match lines, where N and M are positive integers greater than one; and
a priority class detector that is configured to recognize each of the N rows of CAM cells as having different class priority and is further configured to recognize each of the M rows of CAM cells as having a respective class priority that overlaps with a priority class of at least one of the N rows of CAM cells.
10. The CAM device of claim 9 , wherein said priority class detector is configured to recognize each of the M rows of CAM cells as having different class priority.
11. The CAM device of claim 10 , further comprising a priority encoder electrically coupled to said priority class detector; and wherein said priority class detector is configured to recognize a first one of the N rows as having higher priority than all of the M rows and a second one of the N rows as having higher priority than all but one of the M rows.
12. A content addressable memory (CAM) device, comprising:
a priority encoder;
a first tier of CAM arrays arranged side-by-side relative to each other, on a first side of said priority encoder; and
a plurality of priority class detectors that are configured to pass match information from a selected priority class in a selected one of the CAM arrays in said first tier to said priority encoder, with each of said plurality of priority class detectors being disposed between a respective pair of CAM arrays in said first tier.