Method of designing layout of semiconductor device
View Patent ↗This invention provides a method and system for designing the layout of a semiconductor device that appropriately arranges various types of auxiliary cells in vacant areas. The method of the present invention is devised for laying out a plurality of auxiliary cells between logic cells in a semiconductor device. The present invention further provides an apparatus comprising a processor configured to carry out the inventive method. The apparatus of the present invention may include a cell library in which the auxiliary cells are registered and dummy cells are utilized. The present invention additionally provides a computer readable storage medium, containing a program code instructed to perform the method of the present invention.
1. A semiconductor device including a logic cell and auxiliary cells and having a device layout determined by a method for laying out the auxiliary cells in a vacant area that is not occupied by the logic cell in the semiconductor device, wherein each auxiliary cell includes at least one representative auxiliary cell and each auxiliary cell has a predetermined dimension, the semiconductor device being produced by a method comprising:
determining a device layout comprising
temporarily arranging each representative auxiliary cell in the vacant area,
calculating a number of the arranged representative auxiliary cells and a total area of the arranged representative auxiliary cells,
selecting at least one auxiliary cell based on the calculated number, the calculated total area, and a specification of the semiconductor device, and
arranging the selected at least one auxiliary cell in place of the arranged representative auxiliary cells; and
producing the semiconductor device using the determined device layout, wherein all of the arranged representative auxiliary cells are replaced with the auxiliary cells and no representative auxiliary cells remain in the semiconductor device.
2. The semiconductor device according to claim 1 , wherein said arranging the selected at least one auxiliary cell comprises selecting a functional auxiliary cell for each of the temporarily arranged representative auxiliary cells.
3. The semiconductor device according to claim 1 , wherein said temporarily arranging each representative auxiliary cell comprises arranging representative auxiliary cells from largest to smallest in dimension.
4. The semiconductor device according to claim 1 , wherein the auxiliary cells are registered in a cell library and dummy cells are used for temporary arrangement, and wherein each of the dummy cells has only dimension-related data.
5. The semiconductor device according to claim 1 , wherein said arranging the selected at least one auxiliary cell comprises one of the following:
arranging the selected auxiliary cells; and
exchanging the temporarily arranged representative auxiliary cells with the selected auxiliary cells, wherein the exchanged auxiliary cells have the same dimensions as the selected auxiliary cells.
6. The semiconductor device according to claim 5 , wherein the method further comprises deleting the temporarily arranged representative auxiliary cells.
7. A semiconductor device including a logic cell and auxiliary cells and having a device layout determined by a method for laying out the auxiliary cells in a vacant area that is not occupied by the logic cell in the semiconductor device, wherein each auxiliary cell includes at least one representative auxiliary cell and each auxiliary cell has a predetermined dimension, the semiconductor device being produced by a method comprising:
determining a device layout comprising
temporarily arranging each representative auxiliary cell from largest to smallest in dimension, in the vacant area,
calculating a number of the arranged representative auxiliary cells and a total area of the arranged representative auxiliary cells,
selecting at least one auxiliary cell based on the calculated number, the calculated total area, and a specification of the semiconductor device, and
arranging the selected at least one auxiliary cell in place of the arranged representative auxiliary cells; and
producing the semiconductor device using the determined device layout, wherein all of the arranged representative auxiliary cells are replaced with the auxiliary cells and no representative auxiliary cells remain in the semiconductor device.
8. The semiconductor device according to claim 7 , wherein the auxiliary cells are registered in a cell library and have dummy cells for a temporary arrangement, and wherein each of the dummy cells has only dimension-related data.
9. The semiconductor device according to claim 7 , wherein said arranging the selected at least one auxiliary cell comprises one of the following:
arranging the selected auxiliary cells; and
exchanging the temporarily arranged representative auxiliary cells with the selected auxiliary cells, wherein the exchanged representative auxiliary cells have the same dimensions as the selected auxiliary cells.
10. A semiconductor device including a logic cell and auxiliary cells and having a device layout determined by a method for laying out the auxiliary cells in a vacant area that is not occupied by the logic cell in the semiconductor device, wherein the plurality of auxiliary cells include at least one functional auxiliary cell, and the plurality auxiliary cells are categorized into a plurality of groups based on a plurality of dimensions, the semiconductor device being produced by a method comprising:
determining a device layout comprising
temporarily arranging one or more representative auxiliary cells in the vacant area,
calculating a number of the arranged representative auxiliary cells and a total area of the arranged representative auxiliary cells,
selecting one or more of the functional auxiliary cells based on the calculated number, the calculated total area, and a specification of the semiconductor device, and
arranging the selected one or more functional auxiliary cells in place of the arranged representative auxiliary cells; and
producing the semiconductor device using the determined device layout, wherein all of the arranged representative auxiliary cells are replaced with the auxiliary cells and no representative auxiliary cells remain in the semiconductor device.