Word line driver circuit for a content addressable memory
View Patent ↗A word line driver circuit is coupled to a word line of an associated Content Addressable Memory (CAM) array. The word line driver circuit adjusts the word line read voltage in response to a compare signal indicative of whether the CAM array is performing a concurrent compare operation. For some embodiments, the word line driver circuit selectively provides a relatively high word line read voltage or a relatively low word line read voltage in response to the compare signal.
1. A content addressable memory (CAM) array having any number of rows, each of the rows comprising:
a plurality of CAM cells coupled to a word line; and
a word line driver circuit having a first input to receive a decoded address signal, a second input to receive a compare signal, and an output coupled to the word line, the word line driver circuit operable to adjust a read voltage for the word line during a read operation when the compare signal indicates a concurrent compare operation.
2. The CAM array of claim 1 , wherein the word line driver circuit drives the word line with a relatively low read voltage when the compare signal is asserted and drives the word line with a relatively high read voltage when the compare signal is not asserted.
3. A content addressable memory (CAM) array having any number of rows, each of the rows comprising:
a plurality of CAM cells coupled to a word line; and
a word line driver circuit having a first input to receive a decoded address signal, a second input to receive a compare signal, and an output coupled to the word line, the word line driver circuit operable to adjust a read voltage for the word line for a read operation in response to the compare signal, wherein during a read operation the word line driver circuit drives the word line with a relatively low read voltage when there is a concurrent compare operation and drives the word line with a relatively high read voltage when there is not a concurrent compare operation.
4. The CAM array of claim 3 , wherein the compare signal indicates the compare operation.
5. The CAM array of claim 2 , wherein the relatively high read voltage comprises a supply voltage and the relatively low read voltage comprises approximately one transistor threshold voltage below the supply voltage.
6. The CAM array of claim 1 , wherein the word line driver circuit comprises power terminals coupled to a supply voltage and to ground potential.
7. The CAM array of claim 6 , wherein the word line driver circuit comprises:
a first inverter having an input responsive to the decoded address signal, an output coupled to the word line, a first power terminal coupled to ground potential, and a second power terminal;
an NMOS transistor coupled between a supply voltage and the second power terminal and having a gate responsive to the compare signal; and
first and second PMOS transistors coupled in series between the supply voltage and the word line, the first PMOS transistor having a gate responsive to the compare signal and the second PMOS transistor having a gate responsive to the decoded address signal.
8. The CAM array of claim 7 , wherein the inverter comprises a CMOS inverter.
9. The CAM array of claim 7 , further comprising a second inverter having an output coupled to the first inverter and having an input to receive the decoded address signal.
10. The CAM array of claim 1 , wherein the word line driver circuit comprises power terminals coupled to a high supply voltage, to a low supply voltage, and to ground potential.
11. The CAM array of claim 10 , wherein the word line driver circuit comprises:
a first driver having a power terminal coupled to the high voltage supply, an input to receive the decoded address signal, and an output;
a second driver having a power terminal coupled to the low voltage supply, an input to receive the decoded address signal, and an output; and
a multiplexer having inputs coupled to the outputs of the first and second drivers, an output coupled to the word line, and a control terminal to receive the compare signal.
12. The CAM array of claim 1 , wherein the word line driver circuit comprises an address decoder.
13. The CAM array of claim 1 , wherein the word line driver circuit comprises the CAM array.
14. A content addressable memory (CAM) array having any number of rows, each of the rows comprising:
a plurality of CAM cells coupled to a word line;
means for driving the word line during a read operation with a relatively low read voltage if there is a concurrent compare operation and for driving the word line during the read operation with a relatively high read voltage if there is not a concurrent compare operation.
15. The CAM array of claim 14 , wherein a compare signal is asserted when there is a compare operation and is de-asserted when there is not a compare operation.
16. The CAM array of claim 15 , wherein the means for driving comprises:
a first inverter having an input responsive to a decoded address signal, an output coupled to the word line, a first power terminal coupled to ground potential, and a second power terminal;
an NMOS transistor coupled between a supply voltage and the second power terminal and having a gate responsive to the compare signal; and
first and second PMOS transistors coupled in series between the supply voltage and the word line, the first PMOS transistor having a gate responsive to the compare signal and the second PMOS transistor having a gate responsive to the decoded address signal.
17. The CAM array of claim 16 , further comprising a second inverter having an output coupled to the first inverter and having an input to receive the decoded address signal.
18. The CAM array of claim 15 , wherein the means for driving comprises:
a first driver having a power terminal coupled to the high voltage supply, an input to receive the decoded address signal, and an output;
a second driver having a power terminal coupled to the low voltage supply, an input to receive the decoded address signal, and an output; and
a multiplexer having inputs coupled to the outputs of the first and second drivers, an output coupled to the word line, and a control terminal to receive the compare signal.
19. A method for controlling a word line of a content addressable memory (CAM) array, comprising:
providing a compare signal to the array; and
adjusting a read voltage for the word line during a read operation when the compare signal indicates there is a concurrent compare operation.
20. The method of claim 19 , wherein the compare signal is asserted when there is a compare operation and de-asserted when there is not a compare operation.
21. The method of claim 19 , wherein the adjusting comprises:
providing a relatively low word line read voltage when there is a compare operation; and
providing a relatively high word line read voltage when there is not a compare operation.
22. A method of selecting a word line of a content addressable memory (CAM) array for a read operation, comprising:
driving the word line with a relatively low read voltage when there is a concurrent compare operation; and
driving the word line with a relatively high read voltage when there is not a concurrent compare operation.
23. The method of claim 22 , wherein the high read voltage comprises a supply voltage and the low read voltage comprises approximately one transistor threshold voltage below the supply voltage.
24. A method for controlling a word line of a content addressable memory (CAM) array during a read operation, comprising:
enabling a first driver to drive the word line with a relatively low read voltage if there is a concurrent compare operation; and
enabling a second driver to drive the word line with a relatively high read voltage if there is not a concurrent compare operation.
25. The method of claim 24 , further comprising:
disabling the first driver if there is not a concurrent compare operation; and
disabling the second driver if there is a concurrent compare operation.
26. The method of claim 24 , wherein the high read voltage comprises approximately a supply voltage and the low read voltage comprises approximately one transistor threshold voltage below the supply voltage.