Patent Application
Utility
App. No. 10/406,184
· Confirmation No. 9552
Method of manufacturing interconnection structure applied to semiconductor device
Abandoned -- Failure to Respond to an Office Action
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2003-04-04 | TRNA |
Transmittal of New Application | 2 | View | |
| 2003-04-04 | ADS |
Application Data Sheet | 5 | View | |
| 2003-04-04 | A.PE |
Preliminary Amendment | 6 | View | |
| 2003-04-04 | SPEC |
Specification | 9 | View | |
| 2003-04-04 | CLM |
Claims | 2 | View | |
| 2003-04-04 | ABST |
Abstract | 1 | View | |
| 2003-04-04 | DRW |
Drawings-only black and white line drawings | 4 | View | |
| 2003-04-04 | OATH |
Oath or Declaration filed | 4 | View | |
| 2003-04-04 | LET. |
Miscellaneous Incoming Letter | 1 | View |
Inventors
Attorneys & Agents of Record
Classification
USPC
438/627
H10W20/033
Prosecution
- Examiner
- TOLEDO, FERNANDO L
- Art Unit
- 2823
- Customer No.
- 23548
- Docket No.
- 402580
- Confirmation No.
- 9552
Foreign Priority
2002-307324
·
2002-10-22
·
JAPAN
Publication
- Pub. No.
- US20040087137A1
- Pub. Date
- 2004-05-06
No related applications found.
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2004-04-07
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2003-09-10
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2003-04-04
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Quick Facts
- App. No.
- 10/406,184
- Filed
- 2003-04-04
- Pub. No.
- US20040087137A1
- Examiner
- TOLEDO, FERNANDO L
- Art Unit
- 2823
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