Semiconductor device and manufacturing method thereof including a probe test step and a burn-in test step
View Patent ↗Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.
1. The semiconductor device manufacturing method comprising:
a step for forming a number of integrated circuits on a wafer;
a step for implementing a probe test for conductivity on the wafer on which said number of integrated circuits have been formed;
a step for implementing a burn-in thermal load test on the wafer on which said number of integrated circuits have been formed; and
a step for dicing the wafer into a plurality of chips after completion of said probe test step and said burn-in test step,
characterized in that said probe test step/said burn-in test step comprises a pressing step for pressing a plurality of probes provided in a membrane to said wafer by using a plurality of pressure members and that separate pressure loads are respectively applied to said plurality of pressure members on the side opposite said wafer in pressing said plurality of probes.
2. The semiconductor device manufacturing method according to claim 1 , characterized in that one weight is used to apply said pressure loads and in that said plurality of pressure members on the side opposite said wafer are connected with said weight by a plurality of elastic bodies.
3. A semiconductor wafer inspection device comprising:
a plurality of probes to electrically contact a number of integrated circuits on a wafer;
a membrane having a main surface on which said probes are located; and
a plurality of pressure members located on an opposite surface of said membrane from said main surface;
wherein said membrane is applied with separate pressure loads at different locations on said membrane by said plurality of pressure members.
4. A semiconductor device manufacturing method, comprising:
a step for forming a number of integrated circuits on a wafer;
a step for attaching integrated circuit protecting members/external connection terminals to an integrated circuit forming plane of said wafer;
a step for implementing a probe test for conductivity on the wafer on which said number of integrated circuits have been formed;
a step for implementing a burn-in thermal load test on the wafer on which said number of integrated circuits have been formed; and
a step for dicing the wafer into a plurality of chips after completion of said probe test step and said burn-in test step, characterized in that said probe test step/said burn-in test step comprises a pressing step for pressing a plurality of probes provided in a membrane to said wafer by using a plurality of pressure members and that separate pressure loads are respectively applied to said plurality of pressure members on the side opposite said wafer in pressing said plurality of probes.
5. The semiconductor device manufacturing method according to claim 4 , characterized in that one weight is used to apply said pressure loads and in that said plurality of pressure members on the side opposite said wafer are connected with said weight by a plurality of elastic bodies.