Row redundancy memory repair scheme with shift to eliminate timing penalty
A memory having built-in self repair with row shifting is provided. The rows in the memory are divided into smaller row groups and a bad row group is repaired with a redundant row group. Each row group receives a row select signal, which is fed into a shift circuit for the row group and a shift circuit for an adjacent row group. A shift circuit is provided for the redundant row group and the shift circuit for the redundant row group receives the row select signal for only the adjacent row group. If a bad row group is detected, then starting with the row group furthest from the redundant row group, the shift circuit for each row group before the bad row group is deactivated. The row group select signal and word line signal for the bad row group are disabled. The shift circuit for the bad row group and the shift circuit for each row group after the bad row group are activated. Therefore, the bad row group is disabled and the redundant row group fills the void.
1. A method for repairing a bad row group in a memory, wherein the memory includes a plurality of row groups and a test and repair logic, comprising:
testing the plurality of row groups using the test and repair logic;
identifying a first row group from the plurality of row groups as a bad row group using the test and repair logic;
disabling the bad row group using the test and repair logic;
selectively activating a first shift circuit to shift the first row group using the test and repair logic; and
shifting in a redundant row group using the test and repair logic.
2. The method of claim 1 , wherein the step of shifting in a redundant row group includes:
activating the first shift circuit to shift a first row select signal for the first row group to an adjacent row group.
3. The method of claim 1 , wherein the step of shifting in a redundant row group includes:
activating a second shift circuit to shift a second row select signal to a redundant row group.
4. The method of claim 1 , wherein the step of shifting in a redundant row group includes:
selectively activating each shift circuit between the bad row group and the redundant row group.
5. The method of claim 4 , wherein the step of selectively activating each shift circuit between the bad row group and the redundant row group includes generating a shift signal for each shift circuit between the bad row group and the redundant row group.
6. The method of claim 1 , wherein each row group is one row.
7. A memory, comprising:
a plurality of row groups;
a redundant row group;
a plurality of shift circuits, wherein each shift circuit corresponds to a row group; and
a test and repair logic that tests the plurality of row groups, identifies a bad row group from the plurality of row groups, disables the bad row group, selectively activates a first shift circuit from the plurality of shift circuits to shift the first row group, and shifts in a redundant row group.
8. The memory of claim 7 , wherein the test and repair logic activates the first shift circuit to shift a first row select signal for the first row group to an adjacent row group.
9. The memory of claim 7 , wherein the test and repair logic activates a second shift circuit to shift a second row select signal to a redundant row group.
10. The memory of claim 7 , wherein the test and repair logic selectively activates each shift circuit between the bad row group and the redundant row group.
11. The memory of claim 7 , wherein the test and repair logic generates a shift signal for each shift circuit between the bad row group and the redundant row group.
12. The memory of claim 7 , wherein each shift circuit includes a multiplexer.
13. The memory of claim 7 , wherein each row group in the plurality of row groups is one row.