IP Library Assignment 026189/0629
Patent Assignment
Reel/Frame 026189/0629

Change of Name

Recorded: 2011-04-27 Pages: 7
Assignor
LSI LOGIC CORPORATION
Executed: 2007-04-05
Assignee
LSI CORPORATION
1621 BARBER LANE, MS: D-105 LEGAL, MILPITAS, CALIFORNIA, 95035
Covered Properties (18)
Cross-Connected Memory System for Allocating Pool Buffers in Each Frame Buffer and Providing Addresses Thereof
Patent: 5,907,717 →
Application: 08/605,965 →
Cycle Time Reduction Using an Early Precharge
Patent: 6,072,738 →
Application: 09/036,951 →
Formation of Novel Dram Cell Capacitors by Integration of Capacitors with Isolation Trench Sidewalls
Patent: 6,090,661 →
Application: 09/045,633 →
Circuit and Method for Encoding and Retrieving a Bit of Information
Patent: 6,227,637 →
Application: 09/078,746 →
Programmable Moving Inversion Sequencer for Memory Bist Address Generation
Patent: 6,425,103 →
Application: 09/407,412 →
Differential Sense Amplifier with Voltage Margin Enhancement
Patent: 6,225,833 →
Application: 09/426,919 →
Formation of Novel Dram Cell Capacitors by Integration of Capacitors with Isolatiion Trench Sidewalls
Patent: 6,794,698 →
Application: 09/549,265 →
Memory Controller Arbitrating Ras Cas and Bank Precharge Signals
Patent: 6,477,598 →
Application: 09/619,858 →
Memory Testing for Built-in Self-Repair System
Patent: 6,728,910 →
Application: 09/665,749 →
Asynchronous memory self time scheme
Patent: 6,301,176 →
Application: 09/750,214 →
Self-Time Scheme to Reduce Cycle Time for Memories
Patent: 6,483,754 →
Application: 09/859,268 →
Memory Controller with Arbitration Among Several Strobe Requests
Patent: 6,591,323 →
Application: 10/217,769 →
Publication: US 2002/0194448
Memory I/O Buffer Using Shared Read/Write Circuitry
Patent: 6,879,524 →
Application: 10/247,594 →
Publication: US 2004/0057290
Row Redundancy Memory Repair Scheme with Shift Ot Eliminate Timing Penalty
Patent: 6,870,782 →
Application: 10/414,516 →
Publication: US 2004/0208065
Memory Implementation for Handling Integrated Circuit Fabrication Faults
Patent: 7,062,695 →
Application: 10/444,891 →
Publication: US 2004/0237009
Method and System of Testing Data Retention of Memory
Patent: 7,117,408 →
Application: 10/614,642 →
Publication: US 2004/0165415
Wide-Range Programmable Delay Line
Patent: 7,119,596 →
Application: 11/021,361 →
Publication: US 2006/0132210
Latch-Based Random Access Memory (Lbram) with Tri-State Banking and Contention Avoidance
Patent: 7,233,540 →
Application: 11/237,059 →
Related Assignments (25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Feb 23, 1996
From: ELLIS, JACKSON L.
To: SYMBIOS LOGIC INC.
Reel/Frame 007955/0378 →
Assignment of Assignor's Interest Mar 9, 1998
From: BROWN, JEFF S.
To: SYMBIOS, INC.
Reel/Frame 009076/0156 →
Change of Name Mar 10, 1998
From: SYMBIOS LOGIC INC.
To: SYMBIOS, INC .
Reel/Frame 009089/0936 →
Assignment of Assignor's Interest Mar 19, 1998
From: PERNG, DUNG-CHING; LIU, YAUH-CHING
To: LSI LOGIC CORPORATION
Reel/Frame 009069/0929 →
Assignment of Assignor's Interest May 14, 1998
From: PHAN, TUAN
To: LSI LOGIC CORPORATION
Reel/Frame 009185/0594 →
Assignment of Assignor's Interest Oct 2, 1998
From: SYMBIOS, INC.
To: LSI LOGIC CORPORATION
Reel/Frame 009500/0554 →
Assignment of Assignor's Interest Sep 29, 1999
From: PHAN, TUAN
To: LSI LOGIC CORPORATION
Reel/Frame 010297/0506 →
Assignment of Assignor's Interest Oct 26, 1999
From: BROWN, JEFF S.
To: LSI LOGIC CORPORATION
Reel/Frame 010367/0957 →
Assignment of Assignor's Interest Jul 20, 2000
From: YU, LIANG-CHIEN ERIC
To: LSI LOGIC CORPORATION
Reel/Frame 011020/0175 →
Assignment of Assignor's Interest Sep 20, 2000
From: HUANG, JOHNNIE A.
To: LSI LOGIC CORPORATION
Reel/Frame 011136/0376 →
Assignment of Assignor's Interest Dec 27, 2000
From: BROWN, JEFFREY S.
To: LSI LOGIC CORPORATION
Reel/Frame 011417/0385 →
Assignment of Assignor's Interest May 16, 2001
From: AGRAWAL, GHASI R.
To: LSI LOGIC CORPORATION
Reel/Frame 011818/0390 →
Assignment of Assignor's Interest Sep 19, 2002
From: MONZEL, CARL A.
To: LSI LOGIC CORPORATION
Reel/Frame 013314/0096 →
Assignment of Assignor's Interest Apr 15, 2003
From: WU, SIFANG; AGRAWAL, GHASI R.; LECLAIR, KEVIN R.
To: LSI LOGIC CORPORATION
Reel/Frame 013978/0319 →
Assignment of Assignor's Interest May 23, 2003
From: TESTER, DAVID
To: LSI LOGIC CORPORATION
Reel/Frame 014115/0012 →
Assignment of Assignor's Interest Jul 7, 2003
From: DIXIT, CHARUTOSH; SHEN, WILLIAM
To: LSI LOGIC CORPORATION
Reel/Frame 015004/0870 →
Assignment of Assignor's Interest Dec 22, 2004
From: KONG, CHENG-GANG; SUEN, VICTOR
To: LSI LOGIC CORPORATION
Reel/Frame 016126/0650 →
Assignment of Assignor's Interest Sep 27, 2005
From: VINKE, DAVID; OELTJEN, BRET A.; DILLON, MICHAEL N.
To: LSI LOGIC CORPORATION
Reel/Frame 017047/0285 →
Assignment of Assignor's Interest Jul 18, 2011
From: LSI CORPORATION
To: INVENSAS CORPORATION
Reel/Frame 026617/0484 →
Patent Security Agreement May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
Assignment of Assignor's Interest Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
Termination and Release of Security Interest in Patent Rights (Releases Rf 032856-0031) Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
Patent Security Agreement Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
Security Interest Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
Termination and Release of Security Interest in Patents Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →