Latch-based random access memory (LBRAM) with tri-state banking and contention avoidance
A disclosed memory, such as a random access memory (RAM) has multiple banks including a first bank and a second bank each having multiple latch cells configured to store data. The first bank has a first bit line, and the second bank has a second bit line. A first tri-state buffer has an input node coupled to the first bit line, an enable node coupled to receive a first enable signal, and an output node coupled to a tri-state bit line. A second tri-state buffer has an input node coupled to the second bit line, an enable node coupled to receive a second enable signal, and an output node coupled to the tri-state bit line. Enable signal generation logic uses a portion of an address signal to generate the first and second enable signals such that the first and second enable signals are not in an active state simultaneously. Avoiding concurrent activity of the enable signals eliminates contention on the tri-state output bit lines, and thereby prevents the mutually coupled tri-state bit lines output from the first and second tri-state buffers from being active at the same time. Placing a delay between activity minimizes contention on the mutually coupled, buffered bit line.
1. A memory, comprising:
a pair of bit lines addressable within a respective first and second banks of storage cells by a first portion of an address;
an enable signal generation logic adapted to produce a pair of enable signals at non-concurrent times upon the enable signal generation logic receiving a second portion of the address; and
a pair of tri-state buffers coupled to receive respective said pair of bit lines and respective said pair of enable signals, and produce an output from the memory depending on a logic state of the pair of enable signals.
2. The memory as recited in claim 1 , wherein the storage cells comprise a latch.
3. The memory as recited in claim 1 , wherein the second portion of the address comprises at least one lesser significant bit or greater significant bit, and wherein the first portion of the address comprises all bits of the address greater than or less than, respectively, said at least one lesser significant bit or said at least one greater significant bit.
4. A random access memory, comprising:
a plurality of banks including a first bank and a second bank of latch storage cells, wherein the first bank has a first bit line and the second bank has a second bit line;
enable signal generation logic adapted to receive a portion of an address signal and configured to generate a first and second enable signals at dissimilar times dependent upon the portion of the address signals;
a first tri-state buffer coupled to receive the first bit line and the first enable signal;
a second tri-state buffer coupled to receive the second bit line and the second enable signal; and
wherein the first and second tri-state buffers each comprise a tri-state output coupled to one another and configured to produce an output from the memory depending on the address signal and the first and second enable signals.
5. The random access memory as recited in claim 4 , wherein the output signal is indicative of a data value stored in the latch array and accessed via the address signal.
6. The random access memory as recited in claim 4 , wherein the address signal comprises an ordered set of bits, and wherein the enable signal generation logic is adapted to receive one or more of the lowest ordered bits of the address signal and to generate the first and second enable signals dependent upon the one or more of the lowest ordered bits of the address signal.
7. The random access memory as recited in claim 1 , wherein the enable signal generation logic generates the first and second enable signals such that a period of time occurs between a transition of one of the first and second enable signals from an active state to an inactive state and a subsequent transition of the other of the first and second enable signals from the inactive state to the active state.
8. The random access memory as recited in claim 7 , wherein the period of time is greater than or equal to about 40 nanoseconds.
9. The random access memory as recited in claim 7 , wherein the portion of the address signal comprises an address bit signal, and wherein the enable signal generation logic is configured to use the address bit signal to produce a delayed version of the address bit signal, and to generate the first and second enable signals dependent upon both the address bit signal and the delayed version of the address bit signal.
10. The random access memory as recited in claim 9 , wherein the delayed version of the address bit signal is delayed in time by a delay time, and wherein the enable signal generation logic is configured to generate the first and second enable signals such the period of time between the transition of the one of the first and second enable signals from the active state to the inactive state and the subsequent transition of the other of the first and second enable signals from the inactive state to the active state is a portion of the delay time.
11. The random access memory as recited in claim 9 , wherein the enable signal generation logic comprises AND logic coupled to receive the address bit signal and the delayed version of the address bit signal.
12. The random access memory as recited in claim 11 , wherein the AND logic is configured to produce the first and second enable signals.
13. The random access memory as recited in claim 11 , wherein the AND logic is configured to logically AND the address bit signal and the delayed version of the address bit signal to produce an intermediate signal, and wherein the enable signal generation logic is configured to generate the first and second enable signals dependent upon the intermediate signal.
14. The random access memory as recited in claim 9 , wherein the enable signal generation logic comprises a plurality of gates connected in series to produce the delayed version of the address bit signal, and wherein the enable signal generation logic is configured to generate the first and second enable signals such the period of time between the transition of the one of the first and second enable signals from the active state to the inactive state and the subsequent transition of the other of the first and second enable signals from the inactive state to the active state is substantially equal to a delay time of a portion of the gates.
15. The random access memory as recited in claim 14 , wherein the enable signal generation logic comprises a pair of inverter gates connected in series to produce the delayed version of the address bit signal, and wherein the enable signal generation logic is configured to generate the first and second enable signals such the period of time between the transition of the one of the first and second enable signals from the active state to the inactive state and the subsequent transition of the other of the first and second enable signals from the inactive state to the active state is substantially equal to a delay time of one of the inverter gates.
16. The random access memory as recited in claim 4 , wherein the random access memory comprises a latch array divided to form the plurality of banks.
17. The random access memory as recited in claim 16 , wherein the random access memory comprises a 2 n ×m latch array divided to form p banks, wherein n≧1, m≧1, and p≧2.
18. The random access memory as recited in claim 17 , wherein each of the p banks comprises 2 n−k word lines where k=log 2 (p), and wherein the random access memory further comprises p decode units each coupled to the 2 n−k word lines of a corresponding one of the p banks.
19. The random access memory as recited in claim 18 , wherein the address signal comprises an ordered set of n bits, and wherein each of the p decode units is adapted to receive the highest-ordered (n−k) bits of the address signal and to activate one of the 2 n−k word lines of the corresponding one of the p banks dependent upon the highest-ordered (n−k) bits of the address signal.