Patent Assignment
Reel/Frame 014115/0012
Assignment of Assignor's Interest
Recorded: 2003-05-23
Pages: 2
Assignor
TESTER, DAVID
Executed: 2003-05-23
Assignee
LSI LOGIC CORPORATION
1551 MCCARTHY BOULEVARD, INTELLECTUAL PROPERTY LAW DEPARTMENT , M/S D-106, MILPITAS, CALIFORNIA, 95035
Covered Property
(1)
Memory Implementation for Handling Integrated Circuit Fabrication Faults
Related Assignments
(5)
Other recorded transfers of the patent in this record — the chain of ownership.
Change of Name
Apr 27, 2011
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 026189/0629 →
Assignment of Assignor's Interest
Jul 18, 2011
From: LSI CORPORATION
To: INVENSAS CORPORATION
Reel/Frame 026617/0484 →
Security Interest
Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
Security Interest
Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
Release of Security Interest
Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION
Reel/Frame 052920/0001 →