Patent Assignment
Reel/Frame 026617/0484
Assignment of Assignor's Interest
Recorded: 2011-07-18
Pages: 4
Assignor
LSI CORPORATION
Executed: 2011-07-08
Assignee
INVENSAS CORPORATION
3025 ORCHARD PARKWAY, SAN JOSE, CALIFORNIA, 95134
Covered Properties
(20)
Cycle Time Reduction Using an Early Precharge
Patent:
6,072,738 →
Application:
09/036,951 →
Formation of Novel Dram Cell Capacitors by Integration of Capacitors with Isolation Trench Sidewalls
Patent:
6,090,661 →
Application:
09/045,633 →
Circuit and Method for Encoding and Retrieving a Bit of Information
Patent:
6,227,637 →
Application:
09/078,746 →
Dram Cell Having a Vertical Transistor and a Capacitor Formed on the Sidewalls of a Trench Isolation
Patent:
6,177,699 →
Application:
09/083,373 →
Formation of a Novel Dram Cell
Patent:
6,369,418 →
Application:
09/112,687 →
Programmable Moving Inversion Sequencer for Memory Bist Address Generation
Patent:
6,425,103 →
Application:
09/407,412 →
Differential Sense Amplifier with Voltage Margin Enhancement
Patent:
6,225,833 →
Application:
09/426,919 →
Formation of Novel Dram Cell Capacitors by Integration of Capacitors with Isolatiion Trench Sidewalls
Patent:
6,794,698 →
Application:
09/549,265 →
Memory Controller Arbitrating Ras Cas and Bank Precharge Signals
Patent:
6,477,598 →
Application:
09/619,858 →
Memory Testing for Built-in Self-Repair System
Patent:
6,728,910 →
Application:
09/665,749 →
Dram cell having a vertical transistor and a capacitor formed on the sidewalls of a trench isolation
Patent:
6,365,452 →
Application:
09/724,608 →
Asynchronous memory self time scheme
Patent:
6,301,176 →
Application:
09/750,214 →
Self-Time Scheme to Reduce Cycle Time for Memories
Patent:
6,483,754 →
Application:
09/859,268 →
Self-Time Scheme to Reduce Cycle Time for Memories
Patent:
6,643,204 →
Application:
10/209,483 →
Memory Controller with Arbitration Among Several Strobe Requests
Memory I/O Buffer Using Shared Read/Write Circuitry
Row Redundancy Memory Repair Scheme with Shift Ot Eliminate Timing Penalty
Memory Implementation for Handling Integrated Circuit Fabrication Faults
Method and System of Testing Data Retention of Memory
Wide-Range Programmable Delay Line
Related Assignments
(25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Mar 9, 1998
From: BROWN, JEFF S.
To: SYMBIOS, INC.
Reel/Frame 009076/0156 →
Assignment of Assignor's Interest
Mar 19, 1998
From: PERNG, DUNG-CHING; LIU, YAUH-CHING
To: LSI LOGIC CORPORATION
Reel/Frame 009069/0929 →
Assignment of Assignor's Interest
May 14, 1998
From: PHAN, TUAN
To: LSI LOGIC CORPORATION
Reel/Frame 009185/0594 →
Assignment of Assignor's Interest
May 21, 1998
From: PERNG, DUNG-CHING; LIU, YAUH-CHING
To: LSI LOGIC CORPORATION
Reel/Frame 011047/0173 →
Assignment of Assignor's Interest
Jul 9, 1998
From: PERNG, DUNG-CHING; LIU, YAUH-CHING
To: LSI LOGIC CORPORATION
Reel/Frame 009325/0779 →
Assignment of Assignor's Interest
Oct 2, 1998
From: SYMBIOS, INC.
To: LSI LOGIC CORPORATION
Reel/Frame 009500/0554 →
Assignment of Assignor's Interest
Sep 29, 1999
From: PHAN, TUAN
To: LSI LOGIC CORPORATION
Reel/Frame 010297/0506 →
Assignment of Assignor's Interest
Oct 26, 1999
From: BROWN, JEFF S.
To: LSI LOGIC CORPORATION
Reel/Frame 010367/0957 →
Invalid Assignment, See Recording on Reel 011047 Frame 0173 (Re-Record to Correct Recordation Date 05/21/00 to 05/.21/98).
May 21, 2000
From: PERNG, DUNG-CHING; LIU, YAUH-CHING
To: LSI LOGIC CORPORATION
Reel/Frame 011013/0937 →
Assignment of Assignor's Interest
Jul 20, 2000
From: YU, LIANG-CHIEN ERIC
To: LSI LOGIC CORPORATION
Reel/Frame 011020/0175 →
Assignment of Assignor's Interest
Sep 20, 2000
From: HUANG, JOHNNIE A.
To: LSI LOGIC CORPORATION
Reel/Frame 011136/0376 →
Assignment of Assignor's Interest
Dec 27, 2000
From: BROWN, JEFFREY S.
To: LSI LOGIC CORPORATION
Reel/Frame 011417/0385 →
Assignment of Assignor's Interest
May 16, 2001
From: AGRAWAL, GHASI R.
To: LSI LOGIC CORPORATION
Reel/Frame 011818/0390 →
Assignment of Assignor's Interest
Jul 31, 2002
From: AGRAWAL, GHASI R.
To: LSI LOGIC CORPORATION
Reel/Frame 013167/0947 →
Assignment of Assignor's Interest
Sep 19, 2002
From: MONZEL, CARL A.
To: LSI LOGIC CORPORATION
Reel/Frame 013314/0096 →
Assignment of Assignor's Interest
Apr 15, 2003
From: WU, SIFANG; AGRAWAL, GHASI R.; LECLAIR, KEVIN R.
To: LSI LOGIC CORPORATION
Reel/Frame 013978/0319 →
Assignment of Assignor's Interest
May 23, 2003
From: TESTER, DAVID
To: LSI LOGIC CORPORATION
Reel/Frame 014115/0012 →
Assignment of Assignor's Interest
Jul 7, 2003
From: DIXIT, CHARUTOSH; SHEN, WILLIAM
To: LSI LOGIC CORPORATION
Reel/Frame 015004/0870 →
Assignment of Assignor's Interest
Dec 22, 2004
From: KONG, CHENG-GANG; SUEN, VICTOR
To: LSI LOGIC CORPORATION
Reel/Frame 016126/0650 →
Change of Name
Apr 27, 2011
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 026189/0629 →
Change of Name
May 3, 2011
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 026213/0895 →
Assignment of Assignor's Interest
Sep 27, 2013
From: PERNG, DUNG-CHING; LIU, YAUH-CHING
To: LSI LOGIC CORPORATION
Reel/Frame 031352/0459 →
Security Interest
Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
Security Interest
Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
Release of Security Interest
Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION
Reel/Frame 052920/0001 →