Memory implementation for handling integrated circuit fabrication faults
The present invention may provide a circuit generally having a plurality of addressable memory cells and an access control circuit. The access control circuit may be configured to intercept an access to a faulty cell of the plurality of addressable memory cells. The access control circuit may be further configured to redirect the access to a spare cell of the plurality of addressable memory cells.
1. A circuit comprising:
a plurality of addressable memory cells; and
an access control circuit configured to (i) intercept an access to a faulty cell of said plurality of addressable memory cells, and (ii) redirect said access to a spare cell of said plurality of addressable memory cells according to a fault list, wherein said fault list is stored in a non-volatile structure.
2. The circuit of claim 1 , wherein said access control circuit further comprises test circuitry for testing said plurality of addressable memory cells to identify said faulty cell.
3. The circuit of claim 2 , wherein said test circuitry is configured to generate a list comprising said faulty cell.
4. The circuit according to claim 2 , wherein said test circuitry is configured to test each addressable memory cell only once in a first mode and upon each power-up in a second mode.
5. The circuit of claim 1 , wherein said access control circuit is further configured to generate an address map that maps said faulty cell to said spare cell to redirect said access.
6. The circuit of claim 1 , wherein said access control circuit is configured to (i) receive an access address and (ii) compare said access address with a list of addresses for a plurality of said faulty cells.
7. The circuit of claim 6 , wherein said access control circuit is further configured to substitute an address to one of a plurality of said spare cells when said access address is determined to be in said list of addresses.
8. The circuit of claim 1 , wherein said spare cell has an address outside an address range of said access.
9. The circuit of claim 1 , wherein said spare cell is in a subset of said addressable memory cells that is reserved to handle said access when redirected.
10. The circuit of claim 9 , wherein said access control circuitry is further configured to reserve said subset of said addressable memory cells for redirection.
11. The circuit according to claim 1 , wherein said spare cell has a larger physical size than the addressable memory cells.
12. The circuit according to claim 1 , wherein said spare cell is sized to reduce a likelihood of fabrication faults.
13. The circuit according to claim 1 , wherein said plurality of addressable memory cells are configured as a first-in first-out (FIFO) memory.
14. A method of operation in a memory, comprising the steps of:
(a) receiving an address signal as a request for access to a respective memory cell of a plurality of addressable memory cells in said memory;
(b) determining whether said address signal corresponds to a faulty cell in said plurality of addressable memory cells; and
(c) substituting a new address signal for said address signal according to a fault list to access a spare cell of said memory when said address signal is determined to correspond to said faulty cell, wherein said fault list is stored in a non-volatile structure.
15. The method of claim 14 , wherein step (b) comprises the sub-step of:
comparing said address signal with a list of addresses including said faulty cell.
16. The method of claim 14 , further comprising the step of:
testing said plurality of addressable memory cells to identify said faulty cell prior to step (a).
17. The method of claim 14 , further comprising the step of:
generating an address map that maps said faulty cell to said spare cell.
18. The method of claim 14 , further comprising the step of:
accessing said spare cell in response to a control signal.
19. The method of claim 14 , wherein said spare cell has an address outside an address range of said address signal.
20. A method of manufacturing a memory, comprising:
(a) fabricating said memory comprising a plurality of memory cells;
(b) testing said memory after fabrication to determine whether any of said memory cells are a faulty cell;
(c) generating a memory patch to replace each of said faulty cells in an address map of said memory cells with one of a plurality of spare cells; and
(d) storing said memory patch in a non-volatile structure.
21. The method of claim 20 , wherein step (b) comprises the sub-step of:
operating built-in test circuitry in said memory to perform said testing.
22. The method of claim 20 , wherein step (c) comprises the sub-step of:
operating built-in fault handling circuitry in said memory to generate said memory patch.
23. A circuit comprising:
means for receiving an address signal as a request for access to a respective memory cell of a plurality of addressable memory cells in said circuit;
means for determining whether said address signal corresponds to a faulty cell in said plurality of addressable memory cells;
means for substituting a new, address signal for said address signal according to a fault list to access a spare cell of said circuit when said address signal is determined to correspond to said faulty cell, wherein said fault list is stored in a non-volatile structure.