Grooming switch hardware scheduler
View Patent ↗A hardware scheduler for a grooming switch with at least three switching stages accumulates a list of connection requests that cannot be granted given currently granted connection assignments. At a designated time, two data structures are dynamically built: an xRAM which records, for each output of a switch slice, which input is currently assigned to that output; and a yRAM which records, for each of the same outputs, the output of a second switch slice that is connected to a corresponding input of the second switch slice. Connections are assigned to satisfy the stored unassigned requests, by reassigning existing connection assignments using the xRAM and yRAM data structures.
1. A switching method for a grooming switch having at least three switching stages comprising first, middle and last switch stages, the method comprising:
accumulating a list of connection requests which cannot be granted given currently granted connection assignments, said requests for connecting inputs of the first switch stage to outputs of the last switch stage; and
at a designated time, for each request in said list:
dynamically building a first data structure that, for each output of a first switch slice of the middle stage, records a first value representing a configured input of the first switch slice that is currently assigned to said output,
dynamically building a second data structure that records, for each output of the first switch slice of the middle stage, a second value representing an output of a second switch slice of said middle stage that is connected to an input of the second switch slice corresponding to said configured input of the first switch slice, and
assigning connections to satisfy the stored unassigned requests, by reassigning existing connection assignments using the values recorded in the first and the second data structures.
2. The method of claim 1 , the designated time being when the list holds a predetermined number of requests.
3. The method of claim 1 , the designated time being when all requests have been examined.
4. The method of claim 1 , the list being maintained in a buffer.
5. The method of claim 1 , odd-numbered stages comprising time switch slices and even-numbered stages comprising space switch slices.
6. The method of claim 1 , the grooming switch comprising a five-stage Clos network, stages one, three and five being time switches, and stages two and four being space switches.
7. The method of claim 6 , said first, middle and last stages corresponding respectively to stages three, four and five of the Clos network.
8. The method of claim 1 , the method providing rearrangeably non-blocking multicast connections for arbitrary fanouts.
9. The method of claim 1 , there being plural sets of first and second data structures, the method further comprising:
scheduling a connection using a first set of first and second data structures, while a second set of first and second data structures is being dynamically built.
10. The method of claim 1 , each method step being performed by hardware.
11. The method of claim 1 , further comprising:
supporting dual frame alignment.
12. A hardware scheduler for a grooming switch having at least three switching stages comprising first, middle and last switch stages, the hardware scheduler comprising:
a list which accumulates connection requests that cannot be granted given currently granted connection assignments, said requests for connecting inputs of the first switch stage to outputs of the last switch stage;
a first data structure, dynamically constructed for each request in the list at a designated time, that for each output of a first switch slice of the middle stage, records a first value representing a configured input of the first switch slice that is currently assigned to said output;
a second data structure, dynamically constructed for each request at the designated time, that records, for each output of the first switch slice of the middle stage, a second value representing an output of a second switch slice of said middle stage that is connected to an input of the second switch slice corresponding to said configured input of the first switch slice; and
a scheduling engine that assigns connections to satisfy the stored unassigned requests, by reassigning existing connection assignments using the values recorded in the first and the second data structures.
13. The hardware scheduler of claim 12 , the designated time being when the list holds a predetermined number of requests.
14. The hardware scheduler of claim 12 , the designated time being when all requests have been examined.
15. The hardware scheduler of claim 12 , the list being maintained in a buffer.
16. The hardware scheduler of claim 12 , odd-numbered stages comprising time switch slices and even-numbered stages comprising space switch slices.
17. The hardware scheduler of claim 12 , the grooming switch comprising a five-stage Clos network, stages one, three and five being time switches, and stages two and four being space switches.
18. The hardware scheduler of claim 17 , said first, middle and last stages corresponding respectively to stages three, four and five of the Clos network.
19. The hardware scheduler of claim 12 , the rearrangeably non-blocking multicast connections being provided for arbitrary fanouts.
20. The hardware scheduler of claim 12 , further comprising plural sets of first and second data structures, the scheduling engine scheduling a connection using a first set of first and second data structures, while a dynamically building a second set of first and second data structures.
21. The hardware scheduler of claim 12 , the hardware scheduler supporting dual frame alignment.
22. A hardware scheduler for a grooming switch having at least three switching stages comprising first, middle and last switch stages, the hardware scheduler comprising:
means for accumulating a list of connection requests which cannot be granted given currently granted connection assignments, said requests for connecting inputs of the first switch stage to outputs of the last switch stage;
means for dynamically building a first data structure that, for each output of a first switch slice of the middle stage, records a first value representing a configured input of the first switch slice that is currently assigned to said output;
means for dynamically building a second data structure that records, for each output of the first switch slice of the middle stage, a second value representing an output of a second switch slice of said middle stage that is connected to an input of the second switch slice corresponding to said configured input of the first switch slice; and
means for assigning connections to satisfy the stored unassigned requests, including means for reassigning existing connection assignments using the values recorded in the first and the second data structures.
23. The hardware scheduler of claim 22 , wherein at a designated time said first and said second data structures are built for each request in said list.