Method of formation of gate stack spacer and charge storage materials having reduced hydrogen content in charge trapping dielectric flash memory device
View Patent ↗The present invention, in one embodiment, relates to a process for fabricating a charge trapping dielectric flash memory device including steps of providing a semiconductor substrate having formed thereon a gate stack comprising a charge trapping dielectric charge storage layer and a control gate electrode overlying the charge trapping dielectric charge storage layer; forming an oxide layer over at least the gate stack; and depositing a spacer layer over the gate stack, wherein the depositing step deposits a spacer material having a reduced hydrogen content relative to a hydrogen content of a conventional spacer material.
1. A process for fabricating a charge trapping dielectric flash memory device comprising:
providing a semiconductor substrate having formed thereon a bottom oxide layer;
depositing on the bottom oxide layer a charge trapping dielectric charge storage layer, wherein the charge storage layer comprises a charge trapping dielectric material having a reduced hydrogen content relative to a hydrogen content of a conventional charge trapping dielectric storage layer;
depositing on the charge storage layer a top oxide layer;
depositing on the top oxide layer a control gate electrode layer, whereby a gate stack comprising the bottom oxide layer, the charge storage layer, the top oxide layer and the control gate electrode is provided;
forming an oxide layer over at least the gate stack;
depositing a spacer layer over the gate stack, wherein the spacer layer comprises a spacer material having a reduced hydrogen content relative to a hydrogen content of a conventional spacer material; and
etching the spacer layer to form a gate stack spacer adjacent the gate stack,
wherein hydrogen substantially does not migrate into the gate stack from either the gate stack spacer or from the charge storage layer, during subsequent processing or in use.
2. The process of claim 1 , wherein the reduced hydrogen content is achieved by depositing the spacer material and the charge trapping dielectric material using hydrogen-free precursor materials, using atomic layer deposition, using high temperature LPCVD or using a combination of two or more of the foregoing.
3. The process of claim 1 , wherein the reduced hydrogen content is achieved by the spacer material and the charge trapping dielectric material comprising silicon-rich silicon nitride.
4. The process of claim 1 , wherein the reduced hydrogen content is achieved by the spacer material and the charge trapping dielectric material comprising silicon oxynitride, wherein the silicon oxynitride comprises at least about 5 atomic percent oxygen.
5. The process of claim 1 , wherein the reduced hydrogen content is achieved by depositing the spacer material and the charge trapping dielectric material comprising silicon nitride, wherein the depositing step is carried out in the presence of oxygen.
6. The process of claim 5 , wherein sufficient oxygen is present to remove excess hydrogen, but the silicon nitride comprises less than about 5 atomic percent oxygen.
7. The process of claim 1 , wherein at least one of the spacer material and the charge trapping dielectric material comprises a hydrogen content of about 2 atomic percent or less, and the hydrogen content of a conventional spacer material or charge trapping dielectric material is substantially greater than 2 atomic percent.
8. The process of claim 7 , wherein at least one of the spacer material and the charge trapping dielectric material comprises a hydrogen content in the range from about 0.1 atomic percent to about 0.5 atomic percent.
9. The process of claim 1 , wherein hydrogen is substantially not detectable in at least one of the spacer material and the charge trapping dielectric material, when analyzed by FTIR.
10. A process for fabricating a charge trapping dielectric flash memory device comprising:
providing a semiconductor substrate having formed thereon a bottom oxide layer;
depositing on the bottom oxide layer a charge trapping dielectric charge storage layer, wherein the charge storage layer comprises a charge trapping dielectric material having a reduced hydrogen content relative to a hydrogen content of a conventional charge trapping dielectric storage layer;
depositing on the charge storage layer a top oxide layer;
depositing on the top oxide layer a control gate electrode layer, whereby a gate stack comprising the bottom oxide layer, the charge storage layer, the top oxide layer and the control gate electrode is provided;
forming an oxide layer over at least the gate stack;
depositing a spacer layer over the gate stack, wherein the spacer layer comprises a spacer material having a reduced hydrogen content relative to a hydrogen content of a conventional spacer material; and
etching the spacer layer to form a gate stack spacer adjacent the gate stack,
wherein hydrogen substantially does not migrate into the gate stack from either the gate stack spacer or from the charge storage layer, during subsequent processing or in use and both the spacer material and the charge trapping dielectric material comprise a hydrogen content of about 2 atomic percent or less, and the hydrogen content of a conventional spacer material or charge trapping dielectric material is substantially greater than 2 atomic percent.
11. The process of claim 10 , wherein the reduced hydrogen content is achieved by depositing the spacer material and the charge trapping dielectric material using hydrogen-free precursor materials, using atomic layer deposition, using high temperature LPCVD or using a combination of two or more of the foregoing.
12. The process of claim 10 , wherein the reduced hydrogen content is achieved by the spacer material and the charge trapping dielectric material comprising silicon-rich silicon nitride.
13. The process of claim 10 , wherein the reduced hydrogen content is achieved by the spacer material and the charge trapping dielectric material comprising silicon oxynitride, wherein the silicon oxynitride comprises at least about 5 atomic percent oxygen.
14. The process of claim 10 , wherein the reduced hydrogen content is achieved by depositing the spacer material and the charge trapping dielectric material comprising silicon nitride, wherein the depositing step is carried out in the presence of oxygen.
15. The process of claim 14 , wherein sufficient oxygen is present to remove excess hydrogen, but the silicon nitride comprises less than about 5 atomic percent oxygen.
16. The process of claim 10 , wherein at least one of the spacer material and the charge trapping dielectric material comprises a hydrogen content in the range from about 0.1 atomic percent to about 0.5 atomic percent.
17. The process of claim 10 , wherein hydrogen is substantially not detectable in at least one of the spacer material and the charge trapping dielectric material, when analyzed by FTIR.
18. The process of claim 1 wherein at least one of the bottom oxide layer and the top oxide layer comprises a high-K dielectric material or a composite dielectric material.
19. The process of claim 10 wherein at least one of the bottom oxide layer and the top oxide layer comprises a high-K dielectric material or a composite dielectric material.