Method for exposing a semiconductor wafer

1. A method for exposing a semiconductor wafer by adjusting exposure parameters of an exposure tool and projecting a pattern of a matrix configuration of exposure fields on the semiconductor wafer, the method which comprises:

in a first step, dividing the matrix configuration of exposure fields into at least two areas, providing a plurality of sets of exposure parameters including a dose and a focus of the exposure tool, and correlating each of the areas with a different one of the plurality of sets of exposure parameters;

in a second step, exposing each one of the exposure fields using a respective one of the plurality of sets of exposure parameters correlated with a respective one of the areas associated with the one of the exposure fields;

performing the first step and the second step on the semiconductor wafer, which has been coated with a passivation layer and a resist configured on the passivation layer; and

providing each one of the plurality of sets of exposure parameters in accordance with a property of the passivation layer underlying the resist.

2. The method according to claim 1 , which further comprises repeating the second step for a plurality of semiconductor wafers such that an extent and a design of the areas and the plurality of sets of exposure parameters respectively associated with the exposure fields are held constant for all of the plurality of semiconductor wafers.

3. The method according to claim 1 , which further comprises performing the step of dividing the matrix configuration into the areas by:

first, determining for each one of the exposure fields, ranges of a multiplicity of sets of exposure parameters enabling an exposure to achieve a given quality; and

second, associating each one of the exposure fields with a respective one of the areas such that all of the exposure parameters associated with the one of the exposure fields are within the ranges of the multiplicity of sets of exposure parameters.

4. The method according to claim 1 , which further comprises providing the exposure tool as a wafer stepper or scanner.

5. The method according to claim 1 , which further comprises providing the exposure tool as an electron beam lithography tool, a laser beam lithography tool, an ion projection beam lithography tool, or an x-ray lithography tool.

6. The method according to claim 1 , which further comprises:

providing the areas as a continuous outer edge area and a continuous inner area of the semiconductor wafer;

providing a circle separating inner area ones of the exposure fields from outer area ones of the exposure fields; and

providing the circle with an adjustable radius.

7. The method according to claim 1 , which further comprises providing the semiconductor wafer with a diameter of at least 300 millimeters.