Row redundancy in a content addressable memory device
View Patent ↗A content addressable memory (CAM) has a main array including a plurality of rows of CAM cells, one or more spare rows of CAM cells selectable to functionally replace defective rows of CAM cells in the main array, and a control circuit for disabling the defective rows by writing predetermined data to the defective rows of CAM cells.
1. A content addressable memory (CAM) device, comprising:
a main array having any number of rows, each row including a plurality of CAM cells each of which stores a corresponding bit of a data word stored in the row;
one or more spare rows of CAM cells; and
means for functionally replacing a defective row of CAM cells in the main array with one of the spare rows of CAM cells, wherein the means for functionally replacing comprises one or more of the CAM cells in the defective row.
2. The CAM array claim 1 , wherein the means for functionally replacing does not include an additional storage element in the defective row.
3. The CAM device of claim 1 , wherein each row of CAM cells in the main array is coupled to a corresponding main match line, and each spare row of CAM cells is coupled to a corresponding spare match line.
4. The CAM device of claim 1 , wherein one or more of the CAM cells in each row of the main array comprise quaternary CAM cells.
5. The CAM device of claim 4 , wherein one or more of the CAM cells in each spare row comprise quaternary CAM cells.
6. The CAM device of claim 4 , wherein the means for functionally replacing comprises writing a disabling value of “11” to any number of the quaternary CAM cells in the defective row.
7. The CAM device of claim 1 , wherein the means for functionally replacing comprises means for writing disabling data to the defective row.
8. The CAM device of claim 7 , wherein the disabling data forces the defective row to a mismatch state during compare operations.
9. The CAM device of claim 7 , wherein the means for writing comprises a finite state machine (FSM).
10. The CAM device of claim 9 , wherein the means for writing further comprises:
a data multiplexer having a first input to receive input data, a second input to receive the disabling data from the FSM, a control terminal to receive a data select signal from the FSM, and an output coupled to the main array.
11. The CAM device of claim 10 , wherein the means for writing further comprises:
an address multiplexer having a first input to receive an input address, a second input to receive a defective address from the FSM, a control terminal to receive an address select signal from the FSM, and an output to coupled to the main array.
12. The CAM device of claim 11 , wherein the means for writing further comprises:
a spare address decoder coupled to the one or more spare rows and responsive to an enable signal;
a main address decoder coupled to the main array and responsive to a complement of the enable signal;
a table having a plurality of rows, each of the rows for storing an address of a defective row that a corresponding spare row is to functionally replace;
a compare circuit having first inputs coupled to corresponding rows of the table, a second input coupled to the output of the address multiplexer, and outputs to generate address match signals; and
match logic having inputs responsive to the address match signals, and having an output to generate the enable signal.
13. The CAM device of claim 12 , wherein each row in the table includes a valid bit indicating whether the corresponding row stores a valid defective address.
14. The CAM device of claim 12 , wherein the table is externally accessible by a user of the CAM device.
15. The CAM device of claim 1 , further including a priority encoder circuit to generate the index of the highest priority matching entry in the CAM device, the priority encoder circuit adapted to allow each of the spare rows to functionally replace any of the rows in the main array, regardless of priority.
16. A content addressable memory (CAM) device, comprising:
a main array having a plurality of rows of quaternary CAM cells;
one or more spare rows of quaternary CAM cells; and
means for functionally replacing a defective row of CAM cells in the main array with a spare row of CAM cells, wherein the means for functionally replacing comprises the quaternary CAM cells in the defective row.
17. The CAM device of claim 16 , wherein the means for functionally replacing does not include an additional storage element in the defective row.
18. The CAM device of claim 16 , wherein one or more of the CAM cells in each spare row comprise quaternary CAM cells.
19. The CAM device of claim 16 , wherein means for functionally replacing comprises writing disabling data to the quaternary CAM cells in the defective row.
20. The CAM device of claim 19 , wherein the disabling data forces the defective row to a mismatch state during a compare operation.
21. A content addressable memory (CAM) device, comprising:
a main array having a plurality of rows of quaternary CAM cells;
one or more spare rows of CAM cells; and
a row disabling mechanism implemented within one or more of the quaternary CAM cells in each row of the main array.
22. The CAM device of claim 21 , further comprising a table for storing addresses of defective rows in the main array, the table capable of being accessed externally.
23. The CAM device of claim 21 , wherein one or more of the CAM cells in each spare row comprise quaternary CAM cells.
24. The CAM device of claim 21 , wherein the row disabling mechanism does not include storage elements dedicated for disabling the rows of the main array.
25. The CAM device of claim 21 , wherein the row disabling mechanism is enabled by writing disabling data to any number of the CAM cells in a selected row.
26. The CAM device of claim 25 , wherein the disabling data forces the selected row to a mismatch state during a compare operation.
27. The CAM device of claim 21 , wherein each CAM cell in the rows of the main array are configured to either store a corresponding bit of a data word to be compared with a search key during compare operations or to store disabling data that disables the row during compare operations.
28. A content addressable memory (CAM) device, comprising:
a main array having a plurality of rows of quaternary CAM cells; and
one or more spare rows of CAM cells, each of the spare rows selectable to functionally replace a defective row of quaternary CAM cells in the main array,
wherein one or more of the quaternary CAM cells in each row of the main array are configured to implement a row disabling mechanism.
29. The CAM device of claim 28 , further comprising a table for storing addresses of defective rows in the main array, the table capable of being accessed externally.
30. The CAM device of claim 28 , wherein one or more of the CAM cells in the spare rows comprise quaternary CAM cells.
31. The CAM device of claim 28 , wherein the row disabling mechanism does not include storage elements dedicated for disabling the rows of the main array.
32. The CAM device of claim 28 , wherein the row disabling mechanism is enabled by writing disabling data to any number of the CAM cells in a selected row.
33. The CAM device of claim 32 , wherein the disabling data forces the selected row to a mismatch state during a compare operation.
34. The CAM device of claim 28 , wherein each CAM cell in the rows of the main array are configured to either store data to be compared with a search key during compare operations or to store disabling data that disables the row during compare operations.
35. A content addressable memory (CAM) system having a plurality of interconnected CAM modules, each comprising:
a plurality of main rows of quaternary CAM cells, each coupled to a word line and to a match line;
one or more spare rows of quaternary CAM cells, each coupled to a spare word line and to a spate match line; and
means for functionally replacing a defective main row of CAM cells with one of the spare rows of CAM cells, wherein the means for functionally replacing comprises writing a disabling value of “ 11 ” to any number of the quaternary CAM cells in the defective row.
36. The CAM system of claim 35 , wherein the disabling value forces the defective row to a mismatch state during compare operations.
37. The CAM system of claim 35 , wherein the means for functionally replacing comprises a row disabling mechanism implemented within the quaternary CAM cells.
38. The CAM system of claim 35 , wherein the row disabling mechanism is enabled by writing disabling data to any number of the CAM cells in the defective row.
39. A method of functionally replacing a defective row of quaternary content addressable memory (CAM) cells in a CAM array with a spare row of CAM cells, comprising:
storing disabling data in the defective row of CAM cells to disable the defective row; and
enabling the spare row of CAM cells.
40. The method of claim 39 , wherein storing the disabling data comprises:
writing a “ 11 ” value to at least one quaternary CAM cell in the defective row.
41. The method of claim 39 , wherein storing the disabling data comprises:
writing a “ 11 ” value to every quaternary CAM cell in the defective row.
42. The method of claim 39 , wherein the disabling data forces the defective row to a mismatch condition during compare operations.
43. The method of claim 39 , wherein enabling the spare row comprises:
not writing the disabling data to the spare row.
44. The method of claim 39 , further comprising:
writing the disabling data to the CAM cells in the spare row to disable the spare row.
45. A method of functionally replacing a defective row of content addressable memory (CAM) cells in a CAM array with a spare row of CAM cells, comprising:
storing disabling data in each CAM cell in the defective row to disable the defective row; and
enabling the spare row of CAM cells.
46. The method of claim 45 , wherein storing the disabling data comprises:
writing a “11” value to the CAM cells in the defective row.
47. The method of claim 45 , wherein the CAM cells comprise quaternary CAM cells.
48. The method of claim 45 , wherein the disabling data forces the defective row to a mismatch condition during compare operations.
49. The method of claim 45 , wherein enabling the spare row comprises:
not writing the disabling data to the spare row.
50. The method of claim 45 , further comprising:
writing the disabling data to the CAM cells in the spare row to disable the spare row.