IP Library Granted Patent US 6,885,243
Granted Patent B2
US 6,885,243 · App. 10/452,697 · Granted Apr 26, 2005

Dynamic, digitally controlled, temperature compensated voltage reference

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Quick Facts
Patent No.
US 6,885,243
App. No.
10/452,697
Granted
Apr 26, 2005
Kind
B2
Abstract

A voltage reference is dynamically and digitally controlled by a digital function. The digital function may be implemented as a digital calculation or look up table. Inputs to the function include a modifiable trim value stored in a trim register, and a substrate temperature value. The preset value of the trim register is a trim preset value generated by cutting fuses and/or leaving fuses uncut. The cutting may be performed using laser trimming-devices. The output of the digital function is a corrected reference trim value that controls the gain of a voltage reference amplifier whose input is a band gap based voltage reference, and whose output is a derived voltage reference. The substrate temperature value is provided by a monolithic temperature monitor whose sensor may be on the same die as the derived voltage reference. The derived voltage reference provides a stable reference voltage that is dynamically and digitally controllable, to a host system that requires a voltage reference.

Claims (60)

1. A method for digitally controlling a voltage reference, the method comprising:

obtaining an original voltage reference;

generating a trim preset value by performing an initial trimming of the original voltage reference;

generating an intermediate trim value based on the preset trim value;

generating a corrected reference trim value, based on the intermediate trim value and a substrate temperature value; and

setting a gain for a voltage reference amplifier, based on the corrected reference trim value;

wherein said generating the corrected reference trim value is a digitally implemented function;

wherein an input of the voltage reference amplifier is the original voltage reference; and

wherein an output of the voltage reference amplifier is a derived voltage reference.

2. The method of claim 1 further comprising deriving the original voltage reference from a band gap reference.

3. The method of claim 1 , wherein said performing the initial trimming of the original voltage reference comprises one of:

cutting one or more of a plurality of fuses; and

cutting none of the plurality of fuses.

4. The method of claim 3 , wherein said cutting of one or more of the plurality of fuses is accomplished with the use of a laser trimming-device.

5. The method of claim 3 further comprising the plurality of fuses controlling a preset value of a storage element.

6. The method of claim 5 , wherein the storage element is a register.

7. The method of claim 5 , wherein the storage element is a non-volatile memory.

8. The method of claim 5 , wherein the preset value of the storage element is set to the trim preset value.

9. The method of claim 5 further comprising the storage element being read from and written to by one or more of:

a host system; and

a tester.

10. The method of claim 5 further comprising:

storing the intermediate trim value in the storage element; and

providing the intermediate trim value as an output of the storage element.

11. The method of claim 1 , wherein said generating the trim preset value is performed to a default temperature value.

12. The method of claim 1 , wherein said generating the intermediate trim value is performed to an operating temperature range.

13. The method of claim 1 further comprising:

a monolithic temperature-monitor measuring the substrate temperature value; and

the monolithic temperature-monitor providing the substrate temperature value as an input to the digital function.

14. The method of claim 13 , wherein a sensor of the monolithic temperature-monitor is on the same die as the derived voltage reference.

15. A digitally adjusted voltage reference system, the system comprising:

an original voltage reference;

a storage element;

a digital function block; and

a voltage reference amplifier;

wherein the storage element is operable to store an intermediate trim value;

wherein the digital function block is operable to receive the intermediate trim value;

wherein an input of the voltage reference amplifier is the original voltage reference;

wherein the digital function block generates one or more control signals to control a gain of the voltage reference amplifier; and

wherein an output of the voltage reference amplifier is a derived voltage reference.

16. The system of claim 15 , wherein the original voltage reference is derived from a band gap reference.

17. The system of claim 15 further comprising a plurality of fuses;

wherein each fuse of the plurality of fuses is coupled to a respective preset and/or reset input of the storage element;

wherein a trim preset value is generated by performing one of:

cutting one or more of the plurality of fuses; and

cutting none of the plurality of fuses; and

wherein the storage element is operable to receive the trim preset value as an initial value.

18. The system of claim 17 , wherein said cutting one or more of the plurality of fuses is accomplished with the use of a laser trimming-device.

19. The system of claim 15 further comprising a monolithic temperature-monitor;

wherein the monolithic temperature-monitor is operable to measure the substrate temperature value; and

wherein the monolithic temperature-monitor is operable to provide the substrate temperature value as an input to the digital function block.

20. The system of claim 19 , wherein a sensor of the monolithic temperature-monitor is on the same die as the derived voltage reference.

21. The system of claim 15 , wherein the storage element is operable to be read from and written to by one or more of:

a host system; and

a tester.

22. The system of claim 15 , wherein the digital function block comprises one or more algorithms implemented in hardware.

23. The system of claim 15 , wherein the digital function block obtains its output values from one or more lookup tables.

24. The system of claim 15 , wherein the digital function block is user programmable.

25. The system of claim 15 , wherein the storage element comprises one or more D flip-flops.

26. The system of claim 15 , wherein the storage element comprises non-volatile memory.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
MERGER Recorded Dec 11, 2017
From: STANDARD MICROSYSTEMS CORPORATION
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 044820/0715 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2003
From: BURSTEIN, STEVEN; BEKKER, LEN; POPPER, JAY D.
To: STANDARD MICROSYSTEMS CORPORATION
Reel/Frame 014150/0303 →