Direct jitter analysis of binary sampled data
View Patent ↗A technique for determining the timing location and/or jitter of a signal edge includes computing differences between pairs of adjacent samples of the signal edge to yield difference values. First and second statistical moments are computed directly from the difference values, and mean edge location and standard deviation are computed from the first and second moments.
1. An automatic test system for testing a device under test (DUT), comprising:
a timing generator for generating a timing signal that clocks the DUT to produce an output signal and the timing generator for generating a timing signal for activating a sampling strobe; and
a sampling circuit having an input connectable to the DUT for receiving a signal edge of the timing signal and an output arranged to provide a time-ordered plurality of substantially non-averaged samples of the signal edge at instants of time when the sampling strobe is activated;
a processor for computing differences between time-ordered plurality of samples that are proximate in time and for processing the computed differences to determine at least one of a mean, a variance, and a standard deviation in a timing location of the signal edge.
2. An automatic test system as recited in claim 1 , further comprising a memory for storing the time-ordered plurality of substantially non-averaged samples.
3. An automatic test system as recited in claim 1 , wherein the sampling circuit comprises a comparator that generates a 1-bit output.
4. A method of testing edge location and/or jitter on a single signal edge produced by a device under test (DUT), comprising:
accessing a time-ordered plurality of samples indicative of levels of the signal edge at different points in time, wherein at least one of the time-ordered plurality of samples is a non-averaged 1-bit sample;
generating a time-ordered plurality of difference values, each difference value corresponding to a difference between a pair of time-adjacent samples of the time-ordered plurality of samples; and
computing, using a processor, a standard deviation of a timing location of the signal edge from the time-ordered plurality of difference values, wherein the standard deviation is responsive to a second moment of the time-ordered plurality of difference values, the standard deviation indicating a result of the testing;
wherein the step of generating the time-ordered plurality of difference values comprises, for each sample, computing an arithmetic difference between the respective sample and an adjacent sample and dividing the arithmetic difference by an effective sampling period.
5. A method of manufacturing an integrated circuit, comprising:
applying the integrated circuit to an automatic test system;
exercising a test program with the automatic test system for testing the integrated circuit; and
determining whether the integrated circuit passes or fails the test program, wherein the test program performs the steps of
directing the tester to undersample a signal edge from the integrated circuit to produce a time-ordered plurality of samples, wherein at least one of the time-ordered plurality of samples is a non-averaged 1-bit sample;
computing differences between ones of the plurality of samples that are proximate in time; and
processing the computed differences to determine a standard deviation of a single signal edge, wherein the standard deviation is responsive to a second moment of the differences between the plurality of samples that are proximate in time, the standard deviation of the signal edge indicating a result of the test program;
wherein the step of computing differences comprises, for each sample, computing an arithmetic difference between a respective sample and an adjacent sample and dividing the arithmetic difference by an effective sampling period.