Chip and wafer integration process using vertical connections
View Patent ↗A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.
1. A semiconductor structure comprising:
a substrate having a top surface and a bottom surface and a via extending through the substrate;
a first electrical conductor formed in the via;
a first layer overlying the top surface of the substrate, the first layer including a first conducting pad on a top surface of the layer and a second electrical conductor connecting the first conducting pad and the first electrical conductor;
a second conducting pad on the bottom surface of the substrate electrically connected to the first electrical conductor, so that the first conducting pad and the second conducting pad are electrically connected;
a second layer overlying the first layer and having a via formed therein exposing the first conducting pad; and
a plate having a stud formed thereon, the plate overlying the second layer so that the stud is aligned to the via and makes electrical contact with the first conducting pad.
2. A semiconductor structure according to claim 1 , wherein the first electrical conductor has a void formed therein.
3. A semiconductor structure according to claim 2 , wherein the substrate has a first semiconductor device formed in a region of the substrate adjacent to the top surface, and the plate has a second semiconductor device formed therein and electrically connected to the stud.
4. A semiconductor structure according to claim 3 , wherein the first semiconductor device is a DRAM device and the second semiconductor device is a processor.