Longitudinal MISFET manufacturing method, longitudinal MISFET, semiconductor storage device manufacturing method, and semiconductor storage device
View Patent ↗A semiconductor memory device includes a vertical MISFET having a source region, a channel forming region, a drain region, and a gate electrode formed on a sidewall of the channel forming region via a gate insulating film. In manufacturing the semiconductor memory device, the vertical MISFET in which leakage current (off current) is less can be realized by: counter-doping boron of a conductivity type opposite to that of phosphorus diffused into a poly-crystalline silicon film ( 10 ) constituting the channel forming region from an n type poly-crystalline silicon film ( 7 ) constituting the source region of the vertical MISFET, and the above-mentioned poly-crystalline silicon film ( 10 ); and reducing an effective impurity concentration in the poly-crystalline silicon film ( 10 ).
1. A vertical MISFET comprising:
a lower semiconductor layer of a first conductivity type formed over a main surface of a semiconductor substrate;
an intermediate semiconductor layer formed over said lower semiconductor layer, an impurity of a conductivity type opposite to said first conductivity type having been introduced into the intermediate semiconductor layer; and
an upper semiconductor layer of the first conductivity type, the upper semiconductor layer being formed over said intermediate semiconductor layer,
wherein at least said upper semiconductor layer and said intermediate semiconductor layer each have a columnar laminated structure,
said lower semiconductor layer constitutes one of a source and drain of said vertical MISFET, said upper semiconductor layer constitutes the other of the source and drain of said vertical MISFET, a gate electrode of said vertical MISFET is formed on a sidewall of said intermediate semiconductor layer via a gate insulating film, and
a concentration of said impurity introduced into said intermediate semiconductor layer is lower in regions of said intermediate semiconductor layer closer to said lower and upper semiconductor layers and is higher in a region of said intermediate semiconductor layer further from said lower and upper semiconductor layers.
2. The vertical MISFET according to claim 1 ,
wherein a concentration of said impurity introduced into said intermediate semiconductor layer is such that said intermediate semiconductor layer is completely depleted in the condition where a voltage is not applied to said gate electrode.